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PDF ICS843004-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS843004-01 | |
| Descripción | FEMTOCLOCKS- CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS843004-01www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843004-01 is a 4 output LVPECL
ICS synthesizer optimized to generate Ethernet
HiPerClockS™ reference clock frequencies and is a member of
the HiPerClocksTM family of high performance clock
solutions from ICS. Using a 25MHz 18pF parallel
resonant crystal, the following frequencies can be generated
based on the settings of 2 frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz, 62.5MHz. The ICS843004-01 uses
ICS’ 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS843004-01 is packaged
in a small 24-pin TSSOP package.
FEATURES
• Four 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase noise at 156.25MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ............... -95.5 dBc/Hz
1KHz ................ -118 dBc/Hz
10KHz ................ -126 dBc/Hz
100KHz .............. -126.6 dBc/Hz
• Full 3.3V supply mode
• -30°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
F_SEL1
0
F_SEL0
0
Inputs
M Divider N Divider
Value
Value
25 4
M/N
Divider Value
6.25
Output Frequency
(25MHz Ref.)
156.25
0 1 25
5
5
125
10
25
10
2.5
62.5
1 1 25
not used
not used
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
2
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
1
0
M = 25 (fixed)
MR Pulldown
F_SEL[1:0]
0 0 ÷4
0 1 ÷5
1 0 ÷10
1 1 not used
PIN ASSIGNMENT
nQ1
Q1
VCCo
Q0
nQ0
MR
nPLL_SEL
nc
VCCA
F_SEL0
VCC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24 nQ2
23 Q2
2 2 VCCO
21 Q3
20 nQ3
19 VEE
18 VCC
17 nXTAL_SEL
16 TEST_CLK
15 VEE
14 XTAL_IN
13 XTAL_OUT
ICS843004-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0 Top View
nQO
Q1
nQ1
Q2
nQ2
Q3
nQ3
843004AG-01
www.icst.com/products/hiperclocks.html
1
REV. B MAY 6, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS843004-01www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190 100
TYPICAL PHASE NOISE AT 62.5MHZ
10Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.81ps
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
1k
10k 100k
1M 10M
100M
OFFSET FREQUENCY (HZ)
843004AG-01
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
TYPICAL PHASE NOISE AT 125MHZ
10Gb Ethernet Filter
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.63ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
1k 10k 100k 1M 10M
OFFSET FREQUENCY (HZ)
www.icst.com/products/hiperclocks.html
5
100M
REV. B MAY 6, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
ICS843004-01www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
• For logic high, V = V = V – 0.9V
OUT
OH_MAX
CC_MAX
(V - V ) = 0.9V
CCO_MAX OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
– (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX
OH_MAX
L
CC_MAX OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OL_MAX
CC_MAX
L CC_MAX OL_MAX
CC_MAX
OL_MAX
L
CC_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843004AG-01
www.icst.com/products/hiperclocks.html
11
REV. B MAY 6, 2005
11 Page | ||
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