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PDF ICS843001 Data sheet ( Hoja de datos )
| Número de pieza | ICS843001 | |
| Descripción | FEMTO CLOCKS CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS843001 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS843001www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
ICS
The ICS843001 is a Fibre Channel Clock Generator
and a member of the HiPerClocksTM family of high
HiPerClockS™ performance devices from ICS. The ICS843001
uses either a 26.5625MHz or a 23.4375 crystal to
synthesize 106.25MHz, 187.5MHz or 212.5MHz,
using the FREQ_SEL pin. The ICS843001 has excellent <1ps
phase jitter performance, over the 637KHz – 10MHz integration
range. The ICS843001 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
FEATURES
• 1 differential 3.3V LVPECL output
• Crystal oscillator interface designed for 23.4375MHz or
26.5625MHz, 18pF parallel resonant crystal
• Selectable 106.25MHz, 187.5MHz or 212.5MHz
output frequency
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 106.255MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.74ps (typical)
• RMS phase noise at 106.25MHz
Phase noise:
Offset
Noise Power
100Hz ............... -95.2 dBc/Hz
1KHz .............. -118.7 dBc/Hz
10KHz .............. -129.1 dBc/Hz
100KHz .............. -129.6 dBc/Hz
• 3.3V operating supply
• -30°C to 85°C ambient operating temperature
FUNCTION TABLE
Inputs
Crystal Frequency FREQ_SEL
26.5625MHz
0
26.5625MHz
1
23.4375MHz
1
Output Frequencies
106.25MHz (Default)
212.5MHz
187.5MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
FREQ_SEL (Pulldown)
XTAL_IN
XTAL_OUT
OSC
Phase
Detector
VCO
637.5MHz w/
26.5625MHz Ref.
M = ÷24 (fixed)
÷3 1
÷6 0
VCCA 1
8 VCC
VEE 2
7 Q0
XTAL_OUT 3
6 nQ0
nQ0
XTAL_IN 4
5 FREQ_SEL
Q0 ICS843001
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
843001AG
www.icst.com/products/hiperclocks.html
1
REV. B OCTOBER 13, 2004
1 page  
843001AG
Integrated
Circuit
Systems, Inc.
ICS843001www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
TYPICAL PHASE NOISE AT 106.25MHZ
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637Khz to 10MHz = 0.74ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
1k
10k 100k 1M
10M 100M
OFFSET FREQUENCY (HZ)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
TYPICAL PHASE NOISE AT 212.5MHZ
Fibre Channel Filter
212.5MHz
RMS Phase Noise Jitter
637K to 10MHz = 0.67ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
Fibre Channel Filter to raw data
1k 10k 100k 1M
OFFSET FREQUENCY (HZ)
www.icst.com/products/hiperclocks.html
5
10M
100M
REV. B OCTOBER 13, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
ICS843001www.DataSheet4U.com
FEMTOCLOCKS™CRYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
• For logic high, V = V = V – 0.9V
OUT
OH_MAX
CC_MAX
(V - V ) = 0.9V
CCO_MAX OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
– (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX
OH_MAX
L
CC_MAX OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OL_MAX
CC_MAX
L CC_MAX OL_MAX
CC_MAX
OL_MAX
L
CC_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843001AG
www.icst.com/products/hiperclocks.html
11
REV. B OCTOBER 13, 2004
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS843001.PDF ] | |
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