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PDF TDA6508A Data sheet ( Hoja de datos )
| Número de pieza | TDA6508A | |
| Descripción | 3-band mixer/oscillator and PLL | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
TDA6508; TDA6508A; TDA6509;
TDA6509A
3-band mixer/oscillator and PLL for
terrestrial tuners
Product specification
Supersedes data of 2005 Feb 23
2005 Mar 25
1 page  
Philips Semiconductors
3-band mixer/oscillator and PLL for
terrestrial tuners
6 BLOCK DIAGRAM
5 (28)
LOW_RFIN
6 (27)
RF_GND
MID_RFIN1
MID_RFIN2
3 (30)
4 (29)
HIGH_RFIN1
HIGH_RFIN2
1 (32)
2 (31)
RF INPUT
VHF
LOW BAND
RF INPUT
VHF
HIGH BAND
RF INPUT
UHF
BAND
TDA6508
TDA6508A
(TDA6509)
(TDA6509A)
VHF
LOW BAND
MIXER
VHF
HIGH BAND
MIXER
UHF
MIXER
wwwPr.DodautacSthsepeetc4Uifi.ccaotmion
TDA6508; TDA6508A;
TDA6509; TDA6509A
VCC
25 (8)
VHF
LOW BAND
OSCILLATOR
VHF
HIGH BAND
OSCILLATOR
UHF
OSCILLATOR
31 (2)
32 (1)
30 (3)
LOW_OSCOUT
LOW_OSCIN
OSC_GND
28 (5)
29 (4)
MID_OSCIN1
MID_OSCIN2
26 (7)
27 (6)
HIGH_OSCIN1
HIGH_OSCIN2
SYMMETRICAL/ASYMMETRICAL IFAMPLIFIER
FILTER BUFFER WEAK SIGNAL BOOSTER SAW DRIVER
WSB
XTAL_REF
17
(16)
PLL SYNTHESIZER
CRYSTAL
OSCILLATOR
4 MHz
REFERENCE
DIVIDER
64, 80, 128
fref
PHASE
fdiv COMPARATOR
RSA
RSB
15-BIT
PROGRAMMABLE
DIVIDER
IN-LOCK
DETECTOR
CHARGE
PUMP
T0 CP
T1
T2
TUNE
AMP
23 (10)
24 (9)
9 (24)
10 (23)
7 (26)
8 (25)
IFAMP_OUT1
IFAMP_OUT2/
IF_GND
IFAMP_IN1
IFAMP_IN2
MIX_OUT1
MIX_OUT2
19 (14)
20 (13)
CP
VT
SCL 16 (17)
SDA
AS
15 (18)
21 (12)
15-BIT
FREQUENCY
FL REGISTER
I2C-BUS / 3-WIRE BUS
TRANSCEIVER
3-BIT ADC
FL CONTROL
REGISTER
CP T2 T1 T0 RSA RSB WSB
FL fref 1/2fdiv
GATE
T0, T1, T2
PORT
REGISTER
22 (11) PLL_GND
18 (15)
14 (19) 11 (22) 12 (21) 13 (20)
mdb250
ADC/P4
(1) ‘A’ versions only.
The pin numbers in parenthesis refer to versions TDA6509 and TDA6509A.
P3 P2 P1 P0
Fig.1 Block diagram.
2005 Mar 25
5
5 Page 
Philips Semiconductors
3-band mixer/oscillator and PLL for
terrestrial tuners
wwwPr.DodautacSthsepeetc4Uifi.ccaotmion
TDA6508; TDA6508A;
TDA6509; TDA6509A
Table 6 Read data format
NAME
Address byte
Status byte
BYTE
ADB
SB
MSB(1)
1
POR
1
FL
Note
1. MSB is transmitted first.
0
1
BIT
00
11
MA1
A2
MA0
A1
LSB
R/W = 1
A0
Table 7 Description of the bits used in Table 6
BIT
MA1 and MA0
R/W
POR
FL
A2, A1 and A0
DESCRIPTION
programmable address bits; see Table 3
read/write mode selection; 1 = read mode
Power-on reset flag:
0: after end of the first read sequence
1: at Power-on
in-lock flag:
0: loop is not locked
1: loop is locked
digital outputs of the 5-level ADC; see Table 8
Table 8 Digital outputs for analog to digital converter (note 1)
A2
0
0
0
0
1
A1
0
0
1
1
0
A0
0
1
0
1
0
VOLTAGE APPLIED TO PIN ADC
0 VCC to 0.15 VCC
0.15 VCC to 0.3 VCC
0.3 VCC to 0.45 VCC
0.45 VCC to 0.6 VCC
0.6 VCC to 1 VCC
Note
1. Accuracy is ±0.03 × VCC.
8.4 Power-on reset
The threshold level for the power-on reset supply voltage VPOR is set to 3.2 V at room temperature. Below this threshold,
the device is reset to the power-on state.
The following actions take place In the power-on state:
• The charge-pump current is set to 100 µA
• Test bits T2, T1 and T0 are set to logic 001; the charge-pump can either sink or source current
• The Weak signal booster is disabled
• All ports are off and the HIGH band is selected by default.
2005 Mar 25
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA6508A.PDF ] | |
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