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PDF TB502-3X-520-XX Data sheet ( Hoja de datos )
| Número de pieza | TB502-3X-520-XX | |
| Descripción | Test Board | |
| Fabricantes | PhaseLink Corporation | |
| Logotipo |  |
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Test Board for chip evaluation and Layout recommendations
A generic test board for the PLL502-3x and PLL520-0x/-1x/-2x/-3x/-4x/-7x
In order to provide an example of recommended layout for PLL502-3x and PLL520-xx products, PhaseLink provides a
generic test board for these parts. Test boards are available for both TSSOP and SOIC 16 pin components.
In addition, the test board is designed to simplify the testing of the PLL502-3x and PLL520-xx parts. It includes selection
jumpers allowing the user to easily configure the selector pins (connecting them to GND or leaving them unconnected) as
necessary. Depending on the parts under evaluation, these selector pins allow the user to enable or disable the phase
locked loop, or even select a multiplier value (see the datasheet of each part for details).
General Layout recommendations
While this test board achieves satisfactory decoupling results, best results are achieved when the chip or die are laid out
into the final PCB, following the recommendations indicated in the data sheet.
+3.3V
C1
4.7 uf
C2
0.1uf
Vcontrol
Y1
CRYSTAL
R3
0 or 10 ohms
C4
0.1uf
Evaluation Chip
U?
1
2
3
VDDA
XIN
4 XOUT
5
6
S3
S2
7 OE
8 VCON
GNDA
S0
S1
GND
CLKC
VDD
CLKT
GND
GND
16
15
14
13
12
11
10
9
502-38
S0 JP1
1
2
C3
0.1uf
R1
50
C?
0.01 uf
CLKC
R?
26
R?
35
R?
26
-10 db out
S1 JP2
1
2
R2
50
S2 JP3
1
2
S3 JP4
1
2
Vin - PECL
CLKT
C?
0.01 uf
R?
26
R?
35
R?
26
-10 db out
Jumper Selections
NOTE:
1.
2.
For PECL and PECL outputs: 50Ω resistors (R1 and R2) should be installed.
For CMOS output: 50Ω resistors (R1 and R2) should be removed.
In particular, it is essential to include decoupling (by-pass) capacitors as close to the chip as possible in order to minimize
noise sensitivity from the power-supply and thus achieve best phase noise and jitter performance. The generic test board
provides positions for by-pass capacitors (C1, C2, C3) in order to decouple VDD and GND. An additional by-pass capacitor
(C4) is provisioned in order to optimize the signal path coming in from Vcontrol.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 2/20/02 Page 1
1 page | ||
| Páginas | Total 2 Páginas | |
| PDF Descargar | [ Datasheet TB502-3X-520-XX.PDF ] | |
Hoja de datos destacado
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