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PDF 74LVC1G175 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC1G175 | |
| Descripción | Single D-type flip-flop | |
| Fabricantes | NXP Semiconductors | |
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74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Rev. 6 — 11 October 2013
Product data sheet
1. General description
The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.
The master reset (MR) is an asynchronous active LOW input and operates independently
of the clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time
prior to the LOW-to-HIGH clock transition for predictable operation.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.
1 page  
NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
output voltage
Active mode
ambient temperature
Power-down mode; VCC = 0 V
input transition rise and fall rate VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
10. Static characteristics
Min Typ
1.65 -
0-
0-
0-
40 -
--
--
Max
5.5
5.5
VCC
5.5
+125
20
10
Unit
V
V
V
V
C
ns/V
ns/V
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V
0.65 VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2.0
VCC = 4.5 V to 5.5 V
0.7 VCC
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V
-
VCC = 2.3 V to 2.7 V
-
VCC = 2.7 V to 3.6 V
-
VCC = 4.5 V to 5.5 V
-
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
VCC 0.1
IO = 4 mA; VCC = 1.65 V
1.2
IO = 8 mA; VCC = 2.3 V
1.9
IO = 12 mA; VCC = 2.7 V
2.2
IO = 24 mA; VCC = 3.0 V
2.3
IO = 32 mA; VCC = 4.5 V
3.8
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
-
IO = 4 mA; VCC = 1.65 V
-
IO = 8 mA; VCC = 2.3 V
-
IO = 12 mA; VCC = 2.7 V
-
IO = 24 mA; VCC = 3.0 V
-
IO = 32 mA; VCC = 4.5 V
-
II
input leakage current
VCC = 0 V to 5.5 V; VI = 5.5 V or GND [2] -
IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V
-
Typ[1] Max
--
--
--
--
- 0.35 VCC
- 0.7
- 0.8
- 0.3 VCC
--
1.54 -
2.15 -
2.50 -
2.62 -
4.11 -
- 0.10
0.07 0.45
0.12 0.30
0.17 0.40
0.33 0.55
0.39 0.55
0.1 5
0.1 10
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
74LVC1G175
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 11 October 2013
© NXP B.V. 2013. All rights reserved.
5 of 20
5 Page 
NXP Semiconductors
13. Package outline
Plastic surface-mounted package; 6 leads
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
SOT363
DB
E AX
y
6
54
pin 1
index
12
e1 bp
e
3
wM B
HE v M A
A
A1
Q
Lp
detail X
c
01
scale
2 mm
DIMENSIONS (mm are the original dimensions)
UNIT A
A1
max
bp
c
D
E
e
e1 HE Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30 0.25
0.20 0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45 0.25
0.15 0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT363
IEC
REFERENCES
JEDEC
JEITA
SC-88
Fig 10. Package outline SOT363 (SC-88)
74LVC1G175
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 11 October 2013
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
© NXP B.V. 2013. All rights reserved.
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