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PDF EN29SL800 Data sheet ( Hoja de datos )
| Número de pieza | EN29SL800 | |
| Descripción | 8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory Boot Sector Flash Memory CMOS 1.8 Volt-only | |
| Fabricantes | Eon Silicon Solution | |
| Logotipo |  |
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EN29SL800
EN29SL800
8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 1.8 Volt-only
FEATURES
• Single power supply operation
- Full voltage range:1.65-2.2 volt for read and
write operations.
- Ideal for battery-powered applications.
• High performance
- Access times as fast as 70 ns
• Low power consumption (typical values at 5
MHz)
- 15 mA typical active read current
- 15 mA typical program/erase current
- 0.2 μA typical standby current
• Flexible Sector Architecture:
- One 16-Kbyte, two 8-Kbyte, one 32-Kbyte,
and fifteen 64-Kbyte sectors (byte mode)
- One 8-Kword, two 4-Kword, one 16-Kword
and fifteen 32-Kword sectors (word mode)
• Sector protection:
- Hardware locking of sectors to prevent
program or erase operations within individual
sectors
- Additionally, temporary Sector Unprotect
allows code changes in previously locked
sectors.
• High performance program/erase speed
- Byte/Word program time: 5µs/7µs typical
- Sector erase time: 500ms typical
• JEDEC Standard Embedded Erase and
Program Algorithms
• JEDEC standard DATA# polling and toggle
bits feature
• Single Sector and Chip Erase
• Sector Unprotect Mode
• Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
• Low Vcc write inhibit < 1.2V
• Minimum 100K endurance cycle
• Package Options
- 48-pin TSOP (Type 1)
- 48-ball 6mm x 8mm FBGA
- 48-ball 5mm x 6mm WFBGA
- 48-ball 5mm x 6mm WLGA
• Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN29SL800 is an 8-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 1,048,576 bytes or 524,288 words. Any byte can be programmed typically in 5µs. The
EN29SL800 features 1.8V voltage read and write operation, with access time as fast as 70ns to
eliminate the need for WAIT statements in high-performance microprocessor systems.
The EN29SL800 has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full chip erase operation, where each sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions 1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2006/11/06
1 page  
www.DataSheet4U.com
EN29SL800
Sector
TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE
ADDRESS RANGE
(X16)
(X8)
SECTOR
SIZE
(Kbytes / A18 A17 A16 A15 A14 A13 A12
Kwords)
18 7E000h-7FFFFh FC000h-FFFFFh 16/8
111111X
17 7D000h-7DFFFh FA000h-FBFFFh
8/4
1111101
16 7C000h-7CFFFh F8000h-F9FFFh 8/4 1 1 1 1 1 0 0
15 78000h-7BFFFh F0000h – F7FFFh 32/16 1 1 1 1 0 X X
14 70000h-77FFFh E0000h - EFFFFh 64/32 1 1 1 0 X X X
13 68000h-6FFFFh D0000h - DFFFFh 64/32 1 1 0 1 X X X
12 60000h-67FFFh C0000h - CFFFFh 64/32 1 1 0 0 X X X
11 58000h-5FFFFh B0000h - BFFFFh 64/32 1 0 1 1 X X X
10 50000h-57FFFh A0000h - AFFFFh 64/32 1 0 1 0 X X X
9
48000h-4FFFFh 90000h - 9FFFFh 64/32
1 0 0 1XXX
8
40000h-47FFFh 80000h - 8FFFFh 64/32
1 0 0 0XXX
7
38000h-3FFFFh 70000h - 7FFFFh 64/32
0 1 1 1XXX
6
30000h-37FFFh 60000h - 6FFFFh 64/32
0 1 1 0XXX
5
28000h-2FFFFh 50000h – 5FFFFh 64/32
0 1 0 1XXX
4
20000h-27FFFh 40000h – 4FFFFh 64/32
0 1 0 0XXX
3
18000h-1FFFFh 30000h – 3FFFFh 64/32
0 0 1 1XXX
2
10000h-17FFFh 20000h - 2FFFFh 64/32
0 0 1 0XXX
1
08000h-0FFFFh 10000h - 1FFFFh 64/32
0 0 0 1XXX
0
00000h-07FFFh 00000h - 0FFFFh 64/32
0 0 0 0XXX
This Data Sheet may be revised by subsequent versions
5
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. D, Issue Date: 2006/11/06
5 Page 
www.DataSheet4U.com
EN29SL800
The second method is meant for programming equipment. This method requires VID be applied to
both OE# and A9 pin and non-standard microprocessor timings are used. This method is described
in a separate document called EN29SL800 Supplement, which can be obtained by contacting a
representative of Eon Silicon Solution, Inc.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to VID.
During this mode, formerly protected sectors can be programmed
or erased by simply selecting the sector addresses. Once is
removed from the RESET# pin, all the previously protected sectors
are protected again. See accompanying figure and timing
diagrams for more details.
Start
Reset#=VID (note 1)
Perform Erase or Program
Operations
Reset#=VIH
Automatic Sleep Mode
Notes:
1. All protected sectors unprotected.
2. Previously protected sectors protected
again.
Temporary Sector
Unprotect Completed (note 2)
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output is latched and always
available to the system. Icc5 in the DC Characteristics table represents the automatic sleep mode
current specification.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during
Vcc power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when Vcc
is greater than VLKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a
write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE#
are all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE# = VIL, WE# = VIL and OE# = VIH, the device will not accept commands on the rising edge of
WE#.
This Data Sheet may be revised by subsequent versions 11 ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. D, Issue Date: 2006/11/06
11 Page | ||
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