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PDF MAX1422 Data sheet ( Hoja de datos )
| Número de pieza | MAX1422 | |
| Descripción | 12-Bit 20Msps 3.3V Low-Power ADC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-1899; Rev 1; 5/04
www.DataSheet4U.com
12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
General Description
The MAX1422 3.3V, 12-bit analog-to-digital converter
(ADC) features a fully differential input, pipelined, 12-
stage ADC architecture with wideband track-and-hold
(T/H) and digital error correction incorporating a fully-dif-
ferential signal path. The MAX1422 is optimized for low-
power, high dynamic performance applications in
imaging and digital communications. The converter
operates from a single 3.3V supply, consuming only
137mW while delivering a 67dB (typ) signal-to-noise
ratio (SNR) at a 5MHz input frequency and a 20Msps
sampling frequency. The fully-differential input stage
has a small signal -3dB bandwidth of 400MHz and may
be operated with single-ended inputs.
An internal 2.048V precision bandgap reference sets
the ADCs full-scale range. A flexible reference structure
accommodates an internally or externally applied
buffered or unbuffered reference for applications
requiring increased accuracy or a different input volt-
age range.
In addition to low operating power, the MAX1422 features
two power-down modes, a reference power-down, and a
shutdown mode. In reference power-down, the internal
bandgap reference is deactivated, resulting in a 2mA
(typ) supply current reduction. For idle periods, a full
shutdown mode is available to maximize power savings.
The MAX1422 provides parallel, offset binary, CMOS-
compatible three-state outputs.
The MAX1422 is available in a 7mm ✕ 7mm ✕ 1.4mm,
48-pin TQFP package and is specified over the com-
mercial (0°C to +70°C) and extended industrial (-40°C
to +85°C) temperature ranges.
Pin-compatible higher-speed versions of the MAX1422
are also available. Please refer to the MAX1421 data
sheet for 40Msps and the MAX1420 data sheet for
60Msps.
________________________Applications
Medical Ultrasound Imaging
CCD Pixel Processing
Data Acquisition
Radar
IF and Baseband Digitization
Features
♦ Single 3.3V Power Supply
♦ 67dB SNR at fIN = 5MHz
♦ Internal 2.048V Precision Bandgap Reference
♦ Differential Wideband Input T/H Amplifier
♦ Power-Down Modes
130mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
♦ Space-Saving 48-Pin TQFP Package
PART
MAX1422CCM
MAX1422ECM
Ordering Information
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
48 TQFP
48 TQFP
Pin Configuration
AGND
AVDD
AVDD
AGND
AGND
INP
INN
AGND
AGND
AVDD
AVDD
AGND
1
2
3
4
5
6
7
8
9
10
11
12
MAX1422
36 D9
35 D8
34 D7
33 D6
32 DVDD
31 DVDD
30 DGND
29 DGND
28 D5
27 D4
26 D3
25 D2
Functional Diagram appears at end of data sheet.
TQFP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
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12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
Typical Operating Characteristics
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input drive, AIN = -0.5dBFS, fCLK = 20MHz (50% duty
cycle) digital output load CL = 10pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 °C.)
FFT PLOT (4096-POINT DATA RECORD)
0 fIN = 5.2235MHz
-20
-40
-60 HD3
HD2
-80
-100
-120
0
1 2 3 4 5 6 7 8 9 10
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT
(4096-POINT DATA RECORD)
0
fIN1 = 7.0283MHz
fIN2 = 8.0931MHz
-20 fCLK = 20.0056MHz
AIN1 = AIN2 = -6.5dB FS
fIN2
-40
fIN1
-60 IMD2
-80
IMD3
-100
-120
0
1 2 3 4 5 6 7 8 9 10
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
-50
FFT PLOT (4096-POINT DATA RECORD)
0
fIN = 8.1637MHz
-20
-40
-60 HD2 HD3
-80
-100
-120
0
1 2 3 4 5 6 7 8 9 10
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
85
77
69
61
53
45
1
10
ANALOG INPUT FREQUENCY (MHz)
100
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
70
-56 66
-62 62
-68 58
-74 54
-80
1
10
ANALOG INPUT FREQUENCY (MHz)
100
50
1
10
ANALOG INPUT FREQUENCY (MHz)
100
FFT PLOT (4096-POINT DATA RECORD)
0
fIN = 19.8051MHz
-20
-40
HD2
-60 HD3
-80
-100
-120
0
1 2 3 4 5 6 7 8 9 10
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
70
66
62
58
54
50
1
10
ANALOG INPUT FREQUENCY (MHz)
100
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (fIN = 5MHz)
80
70
60
50
40
30
20
10
0
-60
-50 -40 -30 -20 -10
ANALOG INPUT POWER (dB FS)
0
_______________________________________________________________________________________ 5
5 Page 
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12-Bit, 20Msps, 3.3V, Low-Power ADC with
Internal Reference
INP
INN
AVDD
ADC D11–D0
CLK
CLK
AGND
10kΩ
10kΩ
10kΩ
10kΩ
MAX1422
Figure 4. Simplified Clock Input Circuit
log portion of the MAX1421, thereby degrading its
dynamic performance. The use of digital buffers (e.g.
74LVCH16244) on the digital outputs of the ADCs can
further isolate the digital outputs from heavy capacitive
loads. To further improve the MAX1422 dynamic perfor-
mance, add small 100Ω series resistors to the digital
output paths, close to the ADC. Figure 5 displays the
timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1422
samples the analog input signal on the rising edge of
CLK (falling edge of CLK). and output data is valid
seven clock cycles (latency) later. Figure 6 also dis-
plays the relationship between the input clock parame-
ters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AVDD/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associ-
ated with high-speed op amps. Select the RISO and
CIN values to optimize the filter performance and to suit
a particular application. For the application in Figure 7,
a RISO of 50Ω is placed before the capacitive load to
prevent ringing and oscillation. The 22pF CIN capacitor
acts as a small bypassing capacitor.Connecting CIN
from INN to INP may further improve dynamic perfor-
mance.
OE
OUTPUT
DATA D11–D0
tBE
HIGH-Z
VALID DATA
tBD
HIGH-Z
Figure 5. Output Enable Timing
Table 1. MAX1422 Output Code For
Differential Inputs
DIFFERENTIAL
INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
OFFSET BINARY
VREF ✕
2047/2048
+FULL SCALE -
1LSB
VREF ✕
2046/2048
+FULL SCALE -
2LSB
VREF ✕ 1/2048
0
-VREF ✕ 1/2048
-VREF ✕
2046/2048
+1 LSB
Bipolar Zero
-1 LSB
-FULL SCALE
+1 LSB
-VREF ✕
2047/2048
-FULL SCALE
*VREF = VREFP - VREFN
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended signal to a fully dif-
ferential signal, required by the MAX1422 for optimum
performance. Connecting the center tap of the trans-
former to CML provides an AVDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a 1:2 or 1:4
step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1422 provides better SFDR and
THD with fully differential input signals over single-
ended input signals, especially for very high input fre-
quencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to single-
ended mode.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet MAX1422.PDF ] | |
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