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PDF EBE51UD8AGFA Data sheet ( Hoja de datos )

Número de pieza EBE51UD8AGFA
Descripción 512MB Unbuffered DDR2 SDRAM DIMM
Fabricantes Elpida Memory 
Logotipo Elpida Memory Logotipo



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DATA SHEET
www.DataSheet4U.com
512MB Unbuffered DDR2 SDRAM DIMM
EBE51UD8AGFA (64M words × 64 bits, 1 Rank)
Description
The EBE51UD8AGFA is 64M words × 64 bits, 1 rank
DDR2 SDRAM unbuffered module, mounting 8 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
Power supply: VDD = 1.8V ± 0.1V
Data rate: 667Mbps/533Mbps/400Mbps (max.)
SSTL_18 compatible I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(components)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0781E20 (Ver. 2.0)
Date Published October 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005

1 page




EBE51UD8AGFA pdf
EBE51UD8AGFA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 0 60H
1
Module data width
0 1 0 0 0 0 0 0 40H
64
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = 5
-6E
-5C
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 1 0 1 05H
0 0 1 1 0 0 0 0 30H
0 0 1 1 1 1 0 1 3DH
0
SSTL 1.8V
3.0ns*1
3.75ns*1
-4A
SDRAM access from clock (tAC)
-6E
-5C
0 1 0 1 0 0 0 0 50H
0 1 0 0 0 1 0 1 45H
0 1 0 1 0 0 0 0 50H
5.0ns*1
0.45ns*1
0.5ns*1
-4A
0 1 1 0 0 0 0 0 60H
0.6ns*1
DIMM configuration type
0 0 0 0 0 0 0 0 00H
None.
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
None.
Reserved
0 0 0 0 0 0 0 0 00H
0
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
4,8
4
3, 4, 5
4.00mm max.
DIMM type information
0 0 0 0 0 0 1 0 02H
Unbuffered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4
-6E, -5C
0
0
1
1
1
1
0
1
3DH
-4A 0 1 0 1 0 0 0 0 50H
Normal
Weak Driver 50
ODT Support
3.75ns*1
5.0ns*1
Maximum data access time (tAC) from
clock at CL = 4
0 1 0 1 0 0 0 0 50H
-6E, -5C
-4A 0 1 1 0 0 0 0 0 60H
0.5ns*1
0.6ns*1
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
5.0ns*1
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
0.6ns*1
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
15ns
Data Sheet E0781E20 (Ver. 2.0)
5

5 Page





EBE51UD8AGFA arduino
EBE51UD8AGFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
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Parameter
Operating current
(ACT-PRE)
Symbol
IDD0
Grade
-6E
-5C
-4A
Operating current
(ACT-READ-PRE)
IDD1
-6E
-5C
-4A
Precharge power-down
standby current
IDD2P
-6E
-5C
-4A
Precharge quiet standby
current
IDD2Q
-6E
-5C
-4A
Idle standby current
IDD2N
-6E
-5C
-4A
Active power-down
standby current
IDD3P-F
IDD3P-S
-6E
-5C
-4A
-6E
-5C
-4A
Active standby current IDD3N
-6E
-5C
-4A
Operating current
(Burst read operating)
IDD4R
-6E
-5C
-4A
Operating current
(Burst write operating)
IDD4W
-6E
-5C
-4A
max.
920
880
760
1040
1000
880
80
80
64
200
200
160
280
240
200
320
320
280
200
200
160
560
520
480
1840
1520
1200
1760
1520
1200
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0781E20 (Ver. 2.0)
11

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