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PDF EBE51RC4AAFA Data sheet ( Hoja de datos )
| Número de pieza | EBE51RC4AAFA | |
| Descripción | 512MB Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
www.DataSheet4U.com
512MB Registered DDR2 SDRAM DIMM
EBE51RC4AAFA (64M words × 72 bits, 1 Rank)
Description
Features
The EBE51RC4AAFA is a 64M words × 72 bits, 1 rank
DDR2 SDRAM Module, mounting 18 pieces of DDR2
SDRAM sealed in FBGA package. Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 4bits prefetch-pipelined architecture. Data
strobe (DQS and /DQS) both for read and write are
available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay
Locked Loop (DLL) can be set enable or disable. This
module provides high density mounting without utilizing
surface mount technology. Decoupling capacitors are
mounted beside each FBGA on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
• 240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free
• 1.8V power supply
• Data rate: 533Mbps/400Mbps (max.)
• 1.8 V (SSTL_18 compatible) I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Four internal banks for concurrent operation
(Component)
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0471E11 (Ver. 1.1) This product became EOL in April, 2005.
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2006
1 page  
EBE51RC4AAFA
Serial PD Matrix*1
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 0 1 1 0BH
Number of DIMM ranks
0 1 1 0 0 0 0 0 60H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-5C
0 0 1 1 1 1 0 1 3DH
-4A, -4C
0 1 0 1 0 0 0 0 50H
SDRAM access from clock (tAC)
-5C
0 1 0 1 0 0 0 0 50H
-4A, -4C
0 1 1 0 0 0 0 0 60H
DIMM configuration type
0 0 0 0 0 0 1 0 02H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 0 1 0 0 04H
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
Reserved
0 0 0 0 0 0 0 0 00H
DIMM type information
0 0 0 0 0 0 0 1 01H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
SDRAM device attributes: General 0 0 1 1 0 0 0 0 30H
Minimum clock cycle time at CL = 4
0 0 1 1 1 1 0 1 3DH
-5C
-4A, -4C
0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
clock at CL = 4
0 1 0 1 0 0 0 0 50H
-5C
-4A, -4C
0 1 1 0 0 0 0 0 60H
Minimum clock cycle time at CL = 3
0 1 0 1 0 0 0 0 50H
-5C, -4A
-4C 1 1 1 1 1 1 1 1 FFH
Maximum data access time (tAC) from
clock at CL = 3
0 1 1 0 0 0 0 0 60H
-5C, -4A
-4C 1 1 1 1 1 1 1 1 FFH
Comments
128 bytes
256 bytes
DDR2 SDRAM
13
11
1
72
0
SSTL 1.8V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
ECC
7.8µs
×4
×4
0
4,8
4
3, 4, 5
0
Registered
Normal
VDD ± 0.1V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
Undefined*1
0.6ns*1
Undefined*1
Preliminary Data Sheet E0471E11 (Ver. 1.1)
5
5 Page 
EBE51RC4AAFA
DC Characteristics 1 (TC = 0 to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Operating current
(ACT-PRE)
Symbol Grade
max
IDD0
-5C 2440
-4A, -4C 2120
Operating current
(ACT-READ-PRE)
IDD1
-5C 2760
-4A, -4C 2430
Precharge power-down
standby current
IDD2P
-5C
-4A, -4C
700
620
Precharge quiet standby
current
IDD2Q
-5C
-4A, -4C
970
840
Idle standby current
IDD2N
-5C
-4A, -4C
1060
930
Active power-down
standby current
-5C
IDD3P-F
-4A, -4C
1240
1110
-5C
IDD3P-S
-4A, -4C
970
840
Active standby current
-5C
IDD3N
-4A, -4C
1720
1580
Operating current
(Burst read operating)
-5C
IDD4R
-4A, -4C
3660
3060
Operating current
(Burst write operating)
-5C
IDD4W
-4A, -4C
3660
3060
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
mA
STABLE;
Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP
mA (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminary Data Sheet E0471E11 (Ver. 1.1)
11
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