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PDF EBE41UF8ABDA Data sheet ( Hoja de datos )
| Número de pieza | EBE41UF8ABDA | |
| Descripción | 4GB DDR2 SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
4GB DDR2 SDRAM SO-DIMM
EBE41UF8ABDA (512M words × 64 bits, 2 Ranks)
Specifications
• Density: 4GB
• Organization
512M words × 64 bits, 2 ranks
• Mounting 16 pieces of 2G bits DDR2 SDRAM with
sFBGA
• Package: 200-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
(EBE41UF8ABDA-xx-E)
Lead-free (RoHS compliant) and Halogen-free
(EBE41UF8ABDA-xx-F)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E1259E40 (Ver. 4.0)
Date Published October 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
1 page  
EBE41UF8ABDA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 1 0FH
15
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 1 0 0 0 1 71H
Stack/2ranks
Module data width
0 1 0 0 0 0 0 0 40H
64
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = X
-8G (CL = 6)
-6E (CL = 5)
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 1 0 1 05H
0 0 1 0 0 1 0 1 25H
0 0 1 1 0 0 0 0 30H
0
SSTL 1.8V
2.5ns*1
3.0ns*1
SDRAM access from clock (tAC)
-8G
-6E
0 1 0 0 0 0 0 0 40H
0 1 0 0 0 1 0 1 45H
0.4ns*1
0.45ns*1
DIMM configuration type
0 0 0 0 0 0 0 0 00H
None
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
None
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
/CAS latency
-8G
0 1 1 1 0 0 0 0 70H
-6E 0 0 1 1 1 0 0 0 38H
0
4,8
8
4, 5, 6
3, 4, 5
DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H
3.8mm max.
DIMM type information
0 0 0 0 0 1 0 0 04H
SO-DIMM
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
Normal
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at
CL = X − 1
-8G (CL = 5)
0 0 1 1 0 0 0 0 30H
-6E (CL = 4)
0 0 1 1 1 1 0 1 3DH
Maximum data access time (tAC)
from clock at CL = X − 1
-8G (CL = 5)
01
00
01
01
45H
-6E (CL = 4)
0 1 0 1 0 0 0 0 50H
Weak Driver
50Ω ODT Support
3.0ns*1
3.75ns*1
0.45ns*1
0.5ns*1
Minimum clock cycle time at
CL = X − 2
-8G (CL = 4)
-6E (CL = 3)
0 0 1 1 1 1 0 1 3DH
0 1 0 1 0 0 0 0 50H
3.75ns*1
5.0ns*1
Data Sheet E1259E40 (Ver. 4.0)
5
5 Page 
EBE41UF8ABDA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Grade
-8G
-6E
-8G
-6E
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
-8G
-6E
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
-8G
-6E
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
-8G
-6E
Idle standby current
IDD2N
-8G
-6E
Active power-down
standby current
IDD3P-F
IDD3P-S
Active standby current
IDD3N
-8G
-6E
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
-8G
-6E
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
-8G
-6E
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
-8G
-6E
-8G
-6E
max.
800
760
1160
1080
920
880
1280
1200
240
560
480
640
560
560
320
960
880
1480
1320
1840
1640
1480
1320
1840
1640
Unit Test condition
mA one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E1259E40 (Ver. 4.0)
11
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