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PDF EBE41AF4A1QB Data sheet ( Hoja de datos )
| Número de pieza | EBE41AF4A1QB | |
| Descripción | 4GB VLP Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
www.DataSheet4U.com
4GB VLP Registered DDR2 SDRAM DIMM
EBE41AF4A1QB (512M words × 72 bits, 2 Ranks)
Specifications
• Density: 4GB
• Organization
512M words × 72 bits, 2 ranks
• Mounting 18 pieces of 2G bits DDR2 SDRAM with
DDP (FBGA)
DDP: 2 pieces of 1Gb chips sealed in one package
• Package: 240-pin very low profile registered
dual in line memory module (VLP RDIMM)
PCB height: 18.3mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2K bits EEPROM) for
Presence Detect (PD)
Document No. E1246E10 (Ver. 1.0)
Date Published February 2008 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2008
1 page  
EBE41AF4A1QB
Serial PD Matrix
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Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
128 bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256 bytes
2 Memory type
0 0 0 0 1 0 0 0 08H
DDR2 SDRAM
3 Number of row address
0 0 0 0 1 1 1 0 0EH
14
4 Number of column address
0 0 0 0 1 0 1 1 0BH
11
5 Number of DIMM ranks
0 0 0 1 0 0 0 1 11H
2
6 Module data width
0 1 0 0 1 0 0 0 48H
72
7 Module data width continuation
0 0 0 0 0 0 0 0 00H
0
8
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
SSTL 1.8V
9
DDR SDRAM cycle time, CL = X
-8G (CL = 6)
0 0 1 0 0 1 0 1 25H
2.5ns*1
-6E (CL = 5)
0 0 1 1 0 0 0 0 30H
3.0ns*1
SDRAM access from clock (tAC)
10 -8G
-6E
0 1 0 0 0 0 0 0 40H
0 1 0 0 0 1 0 1 45H
0.4ns*1
0.45ns*1
11 DIMM configuration type
0 0 0 0 0 1 1 0 06H
ECC, Address/
command Parity
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
13 Primary SDRAM width
0 0 0 0 0 1 0 0 04H
×4
14 Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
×4
15 Reserved
0 0 0 0 0 0 0 0 00H
0
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
8
SDRAM device attributes:
/CAS latency
18 -8G
0 1 1 1 0 0 0 0 70H
4, 5, 6
-6E
0 0 1 1 1 0 0 0 38H
3, 4, 5
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 1 0 02H
6.00mm max.
20 DIMM type information
0 0 0 0 0 0 0 1 01H
Registered
21 SDRAM module attributes
0 0 0 0 0 0 0 0 00H
Normal
22
SDRAM device attributes: General
0 0 0 0 0 0 1 1 03H
Weak Driver
50Ω ODT Support
Minimum clock cycle time at
CL = X − 1
23 -8G (CL = 5)
0 0 1 1 0 0 0 0 30H
3.0ns*1
-6E (CL = 4)
0 0 1 1 1 1 0 1 3DH
3.75ns*1
Maximum data access time (tAC) from
clock at CL = X − 1
0 1 0 0 0 1 0 1 45H
0.45ns*1
24 -8G (CL = 5)
-6E (CL = 4)
0 1 0 1 0 0 0 0 50H
0.5ns*1
Minimum clock cycle time at
CL = X − 2
25 -8G (CL = 4)
-6E (CL = 3)
0 0 1 1 1 1 0 1 3DH
0 1 0 1 0 0 0 0 50H
3.75ns*1
5.0ns*1
Preliminary Data Sheet E1246E10 (Ver. 1.0)
5
5 Page 
EBE41AF4A1QB
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
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Parameter
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
DDR2-800
DDR2-667
Maximum undershoot area below VSS
DDR2-800
DDR2-667
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDD
Maximum undershoot area below VSS
Maximum peak amplitude allowed for overshoot
Maximum peak amplitude allowed for undershoot
Maximum overshoot area above VDDQ
Maximum undershoot area below VSSQ
Pins
Command, Address,
CKE, ODT
CK, /CK
DQ, DQS, /DQS,
UDQS, /UDQS,
LDQS, /LDQS,
RDQS, /RDQS,
DM, UDM, LDM
Specification
0.5
0.5
0.66
0.8
0.66
0.8
0.5
0.5
0.23
0.23
0.5
0.5
0.23
0.23
Unit
V
V
V-ns
V-ns
V-ns
V-ns
V
V
V-ns
V-ns
V
V
V-ns
V-ns
Volts (V) VDD, VDDQ
VSS, VSSQ
Maximum amplitude
Overshoot area
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Preliminary Data Sheet E1246E10 (Ver. 1.0)
11
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