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PDF EBE21UE8AADA Data sheet ( Hoja de datos )
| Número de pieza | EBE21UE8AADA | |
| Descripción | 2GB DDR2 SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
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PRELIMINARY DATA SHEET
www.DataSheet4U.com
2GB DDR2 SDRAM SO-DIMM
EBE21UE8AADA (256M words × 64 bits, 2 Ranks)
Description
The EBE21UE8AADA is 256M words × 64 bits, 2 ranks
DDR2 SDRAM Small Outline Dual In-line Memory
Module, mounting 16 pieces of 1G bits DDR2 SDRAM
with sFBGA stacking technology. Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 4 bits prefetch-pipelined architecture. Data
strobe (DQS and /DQS) both for read and write are
available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay
Locked Loop (DLL) can be set enable or disable. This
module provides high density mounting without utilizing
surface mount technology. Decoupling capacitors are
mounted beside each SDRAM on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
• 200-pin socket type small outline dual in line memory
module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 533Mbps/400Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(Components)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation.
Document No. E0767E10 (Ver. 1.0)
Date Published August 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
1 page  
EBE21UE8AADA
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 1 0 0 0 08H
Number of row address
0 0 0 0 1 1 1 0 0EH
Number of column address
0 0 0 0 1 0 1 0 0AH
Number of DIMM ranks
0 1 1 1 0 0 0 1 71H
Module data width
0 1 0 0 0 0 0 0 40H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
DDR SDRAM cycle time, CL = 5
-5C
0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
SDRAM access from clock (tAC)
-5C
0 1 0 1 0 0 0 0 50H
-4A 0 1 1 0 0 0 0 0 60H
DIMM configuration type
0 0 0 0 0 0 0 0 00H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
DIMM type information
0 0 0 0 0 1 0 0 04H
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22 SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4
23 -5C
0 0 1 1 1 1 0 1 3DH
-4A 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC) from
24 clock at CL = 4
0 1 0 1 0 0 0 0 50H
-5C
-4A 0 1 1 0 0 0 0 0 60H
25 Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
27 Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
28
Minimum row active to row active
delay (tRRD)
0 0 0 1 1 1 1 0 1EH
29 Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
10
Stack / 2ranks
64
0
SSTL 1.8V
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
None.
7.8µs
×8
None.
0
4,8
8
3, 4, 5
3.80mm max.
SO-DIMM
Normal
Weak Driver
50Ω ODT
Support
3.75ns*1
5.0ns*1
0.5ns*1
0.6ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
Preliminary Data Sheet E0767E10 (Ver. 1.0)
5
5 Page 
EBE21UE8AADA
www.DataSheet4U.com
Parameter
Symbol Grade
max.
Unit Test condition
Auto-refresh current
(Another rank is in IDD2P)
IDD5
Auto-refresh current
(Another rank is in IDD3N)
IDD5
-5C
-4A
-5C
-4A
TBD
TBD
TBD
TBD
tCK = tCK (IDD);
mA Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
mA Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self-refresh current
IDD6
TBD
Self Refresh Mode;
CK and /CK at 0V;
mA CKE ≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD2P)
Operating current
(Bank interleaving)
IDD7
(Another rank is in IDD3N)
-5C
-4A
-5C
-4A
TBD
TBD
TBD
TBD
all bank interleaving reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = tRCD (IDD) −1 × tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1 × tCK (IDD);
CKE is H, CS is H between valid commands;
mA Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN ≤ VIL (AC) (max.)
H is defined as VIN ≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533
DDR2-400
Parameter
4-4-4
3-3-3
CL(IDD)
4
3
tRCD(IDD)
15
15
tRC(IDD)
60
55
tRRD(IDD)
7.5
7.5
tCK(IDD)
3.75
5
tRAS(min.)(IDD)
45
40
tRAS(max.)(IDD)
70000
70000
tRP(IDD)
15
15
tRFC(IDD)
127.5
127.5
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet E0767E10 (Ver. 1.0)
11
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