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PDF EBE21RD4AEFA-6 Data sheet ( Hoja de datos )
| Número de pieza | EBE21RD4AEFA-6 | |
| Descripción | 2GB Registered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
www.DataSheet4U.com
2GB Registered DDR2 SDRAM DIMM
EBE21RD4AEFA-6 (256M words × 72 bits, 2 Ranks)
Description
Features
The EBE21RD4AEFA is a 256M words × 72 bits, 2
ranks DDR2 SDRAM Module, mounting 36 pieces of
512M bits DDR2 SDRAM sealed in FBGA package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 4bits prefetch-pipelined
architecture. Data strobe (DQS and /DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. This module provides high density
mounting without utilizing surface mount technology.
Decoupling capacitors are mounted beside each FBGA
on the module board.
Note: Do not push the cover or drop the modules in
order to avoid mechanical defects, which may
result in electrical defects.
• 240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, data strobe (DQS and /DQS) is
transmitted /received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Burst length: 4, 8
• /CAS latency (CL): 3, 4, 5
• Auto precharge option for each burst access
• Auto refresh and self refresh modes
• Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
• 1 piece of PLL clock driver, 4 piece of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD)
Document No. E0739E11 (Ver. 1.1) This Product became EOL in November, 2006.
Date Published February 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005-2006
1 page  
EBE21RD4AEFA-6
Serial PD Matrix*1
www.DataSheet4U.com
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
2 Memory type
0 0 0 0 1 0 0 0 08H
3 Number of row address
0 0 0 0 1 1 1 0 0EH
4 Number of column address
0 0 0 0 1 0 1 1 0BH
5 Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
6 Module data width
0 1 0 0 1 0 0 0 48H
7 Module data width continuation
0 0 0 0 0 0 0 0 00H
8 Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
9 DDR SDRAM cycle time, CL = 5 0 0 1 1 0 0 0 0 30H
10 SDRAM access from clock (tAC)
0 1 0 0 0 1 0 1 45H
11 DIMM configuration type
0 0 0 0 0 0 1 0 02H
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
13 Primary SDRAM width
0 0 0 0 0 1 0 0 04H
14 Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
15 Reserved
0 0 0 0 0 0 0 0 00H
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
20 DIMM type information
0 0 0 0 0 0 0 1 01H
21 SDRAM module attributes
0 0 0 0 0 0 0 0 00H
22
SDRAM device attributes: General
0 0 0 0 0 0 1 1 03H
23
Minimum clock cycle time at CL = 4
0 0 1 1 1 1 0 1 3DH
24
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
25
Minimum clock cycle time at CL = 3
0 1 0 1 0 0 0 0 50H
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
27
Minimum row precharge time (tRP)
0 0 1 1 1 1 0 0 3CH
28
Minimum row active to row active delay
(tRRD)
0
0
0
1
1
1
1
0
1EH
29 Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
31 Module rank density
0 0 0 0 0 0 0 1 01H
32
Address and command setup time
before clock (tIS)
0 0 1 0 0 0 0 0 20H
33
Address and command hold time after
clock (tIH)
0
0
1
0
1
0
0
0
28H
34 Data input setup time before clock (tDS) 0 0 0 1 0 0 0 0 10H
Comments
128 bytes
256 bytes
DDR2 SDRAM
14
11
2
72
0
SSTL 1.8V
3.0ns*1
0.45ns*1
ECC
7.8µs
×4
×4
0
4,8
4
3, 4, 5
4.00mm max.
Registered
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
45ns
1GB
0.20ns*1
0.28ns*1
0.10ns*1
Data Sheet E0739E11 (Ver. 1.1)
5
5 Page 
EBE21RD4AEFA-6
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
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Parameter
Operating current
(ACT-PRE)
Symbol Grade
max
IDD0
3970
Operating current
(ACT-READ-PRE)
IDD1
4320
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
970
1510
Idle standby current
IDD2N
1870
Active power-down
standby current
IDD3P-F
IDD3P-S
2050
1510
Active standby current
IDD3N
3160
Operating current
(Burst read operating)
IDD4R
Operating current
(Burst write operating)
IDD4W
5620
5440
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
tCK = tCK (IDD);
mA CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
mA
STABLE;
Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0739E11 (Ver. 1.1)
11
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