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PDF EBE11FD8AHFT Data sheet ( Hoja de datos )

Número de pieza EBE11FD8AHFT
Descripción 1GB Fully Buffered DIMM
Fabricantes Elpida Memory 
Logotipo Elpida Memory Logotipo



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No Preview Available ! EBE11FD8AHFT Hoja de datos, Descripción, Manual

PRELIMINARY DATA SHEET
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1GB Fully Buffered DIMM
EBE11FD8AHFT
EBE11FD8AHFE
EBE11FD8AHFL
Specifications
Density: 1GB
Organization
128M words × 72 bits, 2 ranks
Mounting 18 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
Power supply
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V + 0.075V/0.045
Data rate: 667Mbps/533Mbps (max.)
Four internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
JEDEC standard Raw Card B Design
Industry Standard Advanced Memory Buffer (AMB)
High-speed differential point-to-point link interface at
1.5V (JEDEC draft spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
Channel error detection and reporting
Automatic DDR2 SDRAM bus and channel
calibration
SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
System clock
frequency
167MHz
133MHz
FB-DIMM
Speed grade
PC2-5300F
PC2-4200F
Peak channel
throughput
8.0GByte/s
6.4GByte/s
DDR2 SDRAM
FB-DIMM link data rate
4.0Gbps
3.2Gbps
Speed Grade
DDR2-667 (5-5-5)
DDR2-533 (4-4-4)
DDR data rate
667Mbps
533Mbps
Document No. E1000E30 (Ver. 3.0)
Date Published February 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006-2007

1 page




EBE11FD8AHFT pdf
EBE11FD8AHFT, EBE11FD8AHFE, EBE11FD8AHFL
Interfaces
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Figure Block Diagram AMB Interfaces shows the AMB and all of its interfaces. They consist of two FB-DIMM links,
one DDR2 channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host memory controller or
an adjacent FB-DIMM. The DDR2 channel supports direct connection to the DDR2 SDRAMs on a FB-DIMM.
Memory Interface
NB FBD
out Link
SB FBD
in Link
AMB
NB FBD
in Link
SB FBD
out Link
SMB
Block Diagram AMB Interfaces
Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide expansion from a single DIMM per channel to up to 8
DIMMs per channel. The host sends data on the southbound link to the first DIMM where it is received and redriven
to the second DIMM. On the southbound data path each DIMM receives the data and again re-drives the data to the
next DIMM until the last DIMM receives the data. The last DIMM in the chain initiates the transmission of data in the
direction on the host (a.k.a. northbound). On the northbound data path each DIMM receives the data and re-drives
the data to the next DIMM until the host is reached.
Host
Southbound
Nourthbound
AMB
AMB
AMB
AMB
n/c n/c
Block Diagram FB-DIMM Channel Southbound and Northbound Paths
Preliminary Data Sheet E1000E30 (Ver. 3.0)
5

5 Page





EBE11FD8AHFT arduino
EBE11FD8AHFT, EBE11FD8AHFE, EBE11FD8AHFL
AMB Component Timing
For purposes of IDD testing, the following parameters are to be utilized.
Parameter
EI Assertion pass-thru timing
EI deassertion pass-thru timing
Symbol
tEI
propagate
tEID
min. typ.
——
——
EI assertion duration
Resample pass-thru time
tEI 100 —
— TBD
Resynch pass-thru Time
— TBD
Bit lock Interval
tBitLock
——
Frame lock Interval
tFrameLock
Note: 1. The EI stands for Electrical Idle.
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max.
4
bit lock
119
154
Units
clks
clks
clks
ns
ns
frames
frames
Note
Power Specification Parameter and Test Conditions
Frequency (Mbps)
Parameter
Symbol
Idle Current,
single or last
DIMM
Idd_Idle_0
Idle Current, first
DIMM
Idd_Idle_1
Power
Supply
@1.5V
@1.8V
Total
@1.5V
@1.8V
Total
-6E -5C
667 533
max. max. Unit Conditions
Note
2.60
1.44
6.18
2.20
1.33
5.34
A
A
W
L0 state, idle (0 BW)
Primary channel enabled,
Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active.
3.40
1.44
7.43
3.00
1.32
6.58
A
A
W
L0 state, idle (0 BW)
Primary and secondary channels enabled
CKE high. Command and address lines stable.
DRAM clock active.
Active Power
@1.5V
Idd_Active_1 @1.8V
Total
Active Power,
data pass through
Idd_Active_2
@1.5V
@1.8V
Total
Training
@1.5V
Idd_Training
(for AMB spec. @1.8V
Not in SPD)
Total
3.90 3.40 A
2.87 2.85 A
10.93 10.10 W
3.70 3.20 A
1.24 1.17 A
7.52 6.61 W
4.00
1.35
8.20
3.50
1.25
7.23
A
A
W
L0 state
50% DRAM BW, 67% read, 33% write.
Primary and secondary channels enabled.
DRAM clock active, CKE high.
L0 state
50% DRAM BW to downstream DIMM,
67% read, 33% write.
Primary and secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Primary and secondary channels enabled.
100% toggle on all channel lanes
DRAMs idle. 0 BW.
CKE high, Command and address lines stable.
DRAM clock active.
Preliminary Data Sheet E1000E30 (Ver. 3.0)
11

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