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PDF EBE11ED8AEFA-6 Data sheet ( Hoja de datos )
| Número de pieza | EBE11ED8AEFA-6 | |
| Descripción | 1GB Unbuffered DDR2 SDRAM DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
1GB Unbuffered DDR2 SDRAM DIMM
EBE11ED8AEFA-6 (128M words × 72 bits, 2 Ranks)
Description
The EBE11ED8AEFA is 128M words × 72 bits, 2 ranks
DDR2 SDRAM unbuffered module, mounting 18 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
• 240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
Lead-free (RoHS compliant)
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 667Mbps (max.)
• SSTL_18 compatible I/O
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
(components)
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E0725E10 (Ver. 1.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
1 page  
EBE11ED8AEFA-6
Serial PD Matrix
www.DataSheet4U.com
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
Memory type
0 0 0 0 1 0 0 0 08H
128 bytes
256 bytes
DDR2 SDRAM
Number of row address
0 0 0 0 1 1 1 0 0EH
14
Number of column address
0 0 0 0 1 0 1 0 0AH
10
Number of DIMM ranks
0 1 1 0 0 0 0 1 61H
2
Module data width
0 1 0 0 1 0 0 0 48H
72
Module data width continuation
Voltage interface level of this
assembly
DDR SDRAM cycle time, CL = 5
SDRAM access from clock (tAC)
0 0 0 0 0 0 0 0 00H
0 0 0 0 0 1 0 1 05H
0 0 1 1 0 0 0 0 30H
0 1 0 0 0 1 0 1 45H
0
SSTL 1.8V
3.0ns*1
0.45ns*1
DIMM configuration type
0 0 0 0 0 0 1 0 02H
ECC
Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
×8
Reserved
0 0 0 0 0 0 0 0 00H
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
0
4,8
4
3, 4, 5
DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1 01H
4.00mm max.
DIMM type information
0 0 0 0 0 0 1 0 02H
Unbuffered
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
Normal
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1 3DH
Maximum data access time (tAC)
from clock at CL = 4
01
01
00
00
50H
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0 50H
Maximum data access time (tAC)
from clock at CL = 3
01
10
00
00
60H
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0 3CH
Minimum row active to row active
delay (tRRD)
00
01
11
10
1EH
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
Minimum active to precharge time
(tRAS)
0
0
1
0
1
1
0
1
2DH
Module rank density
1 0 0 0 0 0 0 0 80H
Weak Driver
50Ω ODT Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
15ns
45ns
512M bytes
Address and command setup time
before clock (tIS)
0
0
1
0
0
0
0
0
20H
Address and command hold time
after clock (tIH)
0 0 1 0 1 0 0 0 28H
Data input setup time before clock
(tDS)
0
0
0
1
0
0
0
0
10H
Data input hold time after clock (tDH) 0 0 0 1 1 0 0 0 18H
0.20ns*1
0.28ns*1
0.10ns*1
0.18ns*1
Data Sheet E0725E10 (Ver. 1.0)
5
5 Page 
EBE11ED8AEFA-6
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
www.DataSheet4U.com
Parameter
Symbol
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD2P)
Operating current
(ACT-PRE)
IDD0
(Another rank is in IDD3N)
Grade
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD2P)
Operating current
(ACT-READ-PRE)
IDD1
(Another rank is in IDD3N)
max.
1125
1665
1260
1800
Precharge power-down
standby current
IDD2P
180
Precharge quiet standby
current
IDD2Q
450
Idle standby current
IDD2N
Active power-down
standby current
IDD3P-F
IDD3P-S
Active standby current
IDD3N
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD2P)
Operating current
(Burst read operating)
IDD4R
(Another rank is in IDD3N)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD2P)
Operating current
(Burst write operating)
IDD4W
(Another rank is in IDD3N)
Auto-refresh current
(Another rank is in IDD2P)
IDD5
Auto-refresh current
(Another rank is in IDD3N)
IDD5
630
720
450
1260
2160
2700
2070
2610
2520
3060
Unit Test condition
mA
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
mA Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
mA BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
mA Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
mA
tCK = tCK (IDD);
Refresh command at every tRFC (IDD) interval;
CKE is H, /CS is H between valid commands;
mA
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0725E10 (Ver. 1.0)
11
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