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PDF EBE10UE8AFSA Data sheet ( Hoja de datos )
| Número de pieza | EBE10UE8AFSA | |
| Descripción | 1GB DDR2 SDRAM SO-DIMM | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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DATA SHEET
www.DataSheet4U.com
1GB DDR2 SDRAM SO-DIMM
EBE10UE8AFSA (128M words × 64 bits, 1 Rank)
Specifications
• Density: 1GB
• Organization
128M words × 64 bits, 1 rank
• Mounting 8 pieces of 1G bits DDR2 SDRAM sealed
in FBGA
• Package: 200-pin socket type small outline dual in
line memory module (SO-DIMM)
PCB height: 30.0mm
Lead pitch: 0.6mm
Lead-free (RoHS compliant) and Halogen-free
• Power supply: VDD = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• Eight internal banks for concurrent operation
(components)
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C ≤ TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
• Operating case temperature range
TC = 0°C to +95°C
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• /DQS can be disabled for single-ended Data Strobe
operation
Document No. E1450E20 (Ver.2.0)
Date Published July 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2009
1 page  
EBE10UE8AFSA
Serial PD Matrix
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Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128 bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256 bytes
2 Memory type
0 0 0 0 1 0 0 0 08H
DDR2 SDRAM
3 Number of row address
0 0 0 0 1 1 1 0 0EH
14
4 Number of column address
0 0 0 0 1 0 1 0 0AH
10
5 Number of DIMM ranks
0 1 1 0 0 0 0 0 60H
1
6 Module data width
0 1 0 0 0 0 0 0 40H
64
7
Module data width continuation
0 0 0 0 0 0 0 0 00H
0
8
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
SSTL 1.8V
9
DDR SDRAM cycle time, CL = X
-8G (CL = 6)
0 0 1 0 0 1 0 1 25H
2.5ns*1
-6E (CL = 5)
0 0 1 1 0 0 0 0 30H
3.0ns*1
10
SDRAM access from clock (tAC)
-8G
0 1 0 0 0 0 0 0 40H
0.4ns*1
-6E
0 1 0 0 0 1 0 1 45H
0.45ns*1
11 DIMM configuration type
0 0 0 0 0 0 0 0 00H
None
12 Refresh rate/type
1 0 0 0 0 0 1 0 82H
7.8µs
13 Primary SDRAM width
0 0 0 0 1 0 0 0 08H
×8
14 Error checking SDRAM width
0 0 0 0 0 0 0 0 00H
None
15 Reserved
0 0 0 0 0 0 0 0 00H
0
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
8
SDRAM device attributes: /CAS
18 latency
0 1 1 1 0 0 0 0 70H
4, 5, 6
-8G
-6E
0 0 1 1 1 0 0 0 38H
3, 4, 5
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 0 1 01H
3.80mm max.
20 DIMM type information
0 0 0 0 0 1 0 0 04H
SO-DIMM
21 SDRAM module attributes
0 0 0 0 0 0 0 0 00H
Normal
22
SDRAM device attributes: General 0 0 0 0 0 0 1 1 03H
Weak Driver
50Ω ODT Support
Minimum clock cycle time at
23 CL = X − 1
0 0 1 1 0 0 0 0 30H
3.0ns*1
-8G (CL = 5)
-6E (CL = 4)
0 0 1 1 1 1 0 1 3DH
3.75ns*1
Maximum data access time (tAC) from
24 clock at CL = X − 1
0 1 0 0 0 1 0 1 45H
0.45ns*1
-8G (CL = 5)
-6E (CL = 4)
0 1 0 1 0 0 0 0 50H
0.5ns*1
Minimum clock cycle time at
25 CL = X − 2
-8G (CL = 4)
-6E (CL = 3)
0 0 1 1 1 1 0 1 3DH
0 1 0 1 0 0 0 0 50H
3.75ns*1
5.0ns*1
Data Sheet E1450E20 (Ver. 2.0)
5
5 Page 
EBE10UE8AFSA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
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Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-8G
-6E
Operating current
(ACT-READ-PRE)
IDD1
-8G
-6E
Precharge power-down
standby current
IDD2P
Precharge quiet standby
current
IDD2Q
-8G
-6E
Idle standby current
IDD2N
-8G
-6E
Active power-down
standby current
IDD3P-F
IDD3P-S
Active standby current
IDD3N
-8G
-6E
Operating current
(Burst read operating)
IDD4R
-8G
-6E
Operating current
(Burst write operating)
IDD4W
-8G
-6E
max.
680
640
800
760
80
280
240
320
280
280
160
720
640
1280
1120
1280
1120
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING MRS(12) = 1
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E1450E20 (Ver. 2.0)
11
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