|
|
Numéro de référence | IDT5T93GL06 | ||
Description | 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II | ||
Fabricant | Integrated Device Technology | ||
Logo | |||
IDT5T93GL06
2.5VLVDS1:6GLITCHLESSCLOCKBUFFERTERABUFFERII
2.5V LVDS 1:6 GLITCHLESS
CLOCK BUFFER
TERABUFFER™ II
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RU.EcRoAmNGE
IDT5T93GL06
FEATURES:
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 100ps (max)
• High speed propagation delay < 2ns (max)
• Up to 800MHz operation
• Glitchless input clock switching up to 650MHz
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V),
CML, or LVDS input interface
• Selectable differential inputs to six LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package
APPLICATIONS:
• Clock distribution
DESCRIPTION:
The IDT5T93GL06 2.5V differential clock buffer is a user-selectable differ-
entialinputtosixLVDSoutputs. ThefanoutfromadifferentialinputtosixLVDS
outputs reduces loading on the preceding driver and provides an efficient clock
distributionnetwork. TheIDT5T93GL06canactasatranslatorfromadifferential
HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to
LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to
translatetoLVDSoutputs. Theredundantinputcapabilityallowsforaglitchless
change-over from a primary clock source to a secondary clock source up to
650MHz. Selectable inputs are controlled by SEL. During the switchover, the
output will disable low for up to three clock cycles of the previously-selected input
clock. The outputs will remain low for up to three clock cycles of the newly-
selected clock, after which the outputs will start from the newly-selected input.
A FSEL pin has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum specifications.
The IDT5T93GL06 outputs can be asynchronously enabled/disabled.
Whendisabled,theoutputswilldrivetothevalueselectedbytheGLpin. Multiple
power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
GL
G
PD
A1
A1
A2
A2
SEL
FSEL
1
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2003 Integrated Device Technology, Inc.
1
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
OCTOBER 2003
DSC-6183/8
|
|||
Pages | Pages 15 | ||
Télécharger | [ IDT5T93GL06 ] |
No | Description détaillée | Fabricant |
IDT5T93GL02 | 2.5V LVDS 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II | Integrated Device Technology |
IDT5T93GL04 | 2.5V LVDS 1:4 GLITCHLESS CLOCK BUFFER TERABUFFER II | Integrated Device Technology |
IDT5T93GL06 | 2.5V LVDS 1:6 GLITCHLESS CLOCK BUFFER TERABUFFER II | Integrated Device Technology |
US18650VTC5A | Lithium-Ion Battery | Sony |
TSPC106 | PCI Bus Bridge Memory Controller | ATMEL |
TP9380 | NPN SILICON RF POWER TRANSISTOR | Advanced Semiconductor |
www.DataSheetWiki.com | 2020 | Contactez-nous | Recherche |