IDT74FCT20807 Datasheet PDF - Integrated Device Technology
| Part Number | IDT74FCT20807 | |
| Description | 2.5V CMOS 1-TO-10 CLOCK DRIVER | |
| Manufacturers | Integrated Device Technology | |
| Logo |  |
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IDT74FCT20807
2.5V CMOS 1-TO-10 CLOCK DRIVER
2.5V CMOS
1-TO-10 CLOCK DRIVER
INDUSTRIALTEMPERATURERANGE
www.DataSheet4U.com
IDT74FCT20807
FEATURES:
• High frequency > 150MHz
• Guaranteed low skew < 150ps (max.) between any two outputs
• Very low duty cycle distortion < 300ps
• High speed: propagation delay < 3ns
• Very low CMOS power levels
• TTL compatible inputs and outputs
• 1:10 fanout
• Maximum output rise and fall time < 1.25ns (max.)
• Low input capacitance: 3pF typical
• 2.5V supply voltage
• Available in SSOP and QSOP packages
DESCRIPTION:
The FCT20807 is a 2.5V compatible, high speed, low noise, 1:10 fanout,
non-invertingclockbuffer. Thelargefanoutfromasingleinputreducesloading
on the preceding driver and provides an efficient clock distribution network.
Providing output to output skew as low as 150ps, the FCT20807 is an ideal clock
distribution device for synchronous systems. Multiple power and grounds
reduce noise. Typical applications are clock and signal distribution.
FUNCTIONAL BLOCK DIAGRAM
O1
O2
O3
O4
O5
IN
O6
O7
O8
O9
O10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2003 Integrated Device Technology, Inc.
PIN CONFIGURATION
IN
GND
O1
VCC
O2
GND
O3
VCC
O4
GND
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
SSOP/ QSOP
TOP VIEW
VCC
O10
O9
GND
O8
VCC
O7
GND
O6
O5
FEBRUARY 2003
1
DSC - 6171/12
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IDT74FCT20807
2.5V CMOS 1-TO-10 CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
VCC
Pulse
Generator
VIN VOUT
D.U.T.
CL
CL = Load Capacitance: Includes Jig and Probe Capacitance
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INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK(o)
tSK(o)
tPLH2
tPHL2
2.5V
1.25V
0V
VOH
1.25V
VOL
VOH
1.25V
VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Output Skew - tSK(O)
INPUT
OUTPUT
tPLH
tPHL
tR tF
Propagation Delay
2.5V
1.25V
0V
VOH
1.7V
1.25V
0.7V VOL
INPUT
DEVICE 1 OUTPUT
DEVICE 2 OUTPUT
tPLH1
tPHL1
tSK(t)
tSK(t)
tPLH2
tPHL2
2.5V
1.25V
0V
VOH
1.25V
VOL
VOH
1.25V
VOL
tSK(t) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Part-to-Part Skew - tSK(PP)
NOTE: Device 1 and device 2 are same package type and speed grade.
INPUT
OUTPUT
tPLH
tPHL
tSK(p) = |tPHL - tPLH|
Pulse Skew - tSK(P)
2.5V
1.25V
0V
VOH
1.25V
VOL
TEST CONDITIONS
Symbol
CL
VCC = 2.5V ±0.2V
22(1)
12(2)
RT
tR / tF
ZOUT of pulse generator
1.25(1)
1.2(2)
Unit
pF
Ω
ns
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
NOTES:
1. Test conditions at 100MHz.
2. Test conditions at 150MHz.
5
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| Information | Total 6 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IDT74FCT20807.PDF Datasheet ] | |
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