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PDF IDT74FST163211 Data sheet ( Hoja de datos )
| Número de pieza | IDT74FST163211 | |
| Descripción | 24-BIT BUS SWITCH | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74FST163211
24-BIT BUS SWITCH
24-BIT BUS SWITCH
INDUSTRwIAwLwT.EDMaPtaESRheAeTtU4RU.EcRomANGE
IDT74FST163211
FEATURES:
• Bus switches provide zero delay paths
• Low switch on-resistance; 5Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• Available in TSSOP package
DESCRIPTION:
The FST163211 belongs to IDT's family of Bus switches. Bus switch
devices perform the function of connecting or isolating two ports without
providing any inherent current sink or source capability. Thus they
generate little or no noise of their own while providing a low resistance path
for an external driver. These devices connect input and output ports through
an n-channel FET. When the gate-to-source junction of this FET is
adequately forward-biased, the device conducts and the resistance be-
tween input and output ports is small. Without adequate bias on the gate-
to-source junction of the FET, the FET is turned off, therefore with no VCC
applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection between input and
output ports reduces the delay in this path to close to zero.
FUNCTIONAL BLOCK DIAGRAM
1A1
1B1
1A12
2A1
1B12
2B1
2A12
1OE
2OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
2B12
JANUARY 2004
DSC-3685/3
1 page  
IDT74FST163211
24-BIT BUS SWITCH
TEST CIRCUITS AND WAVEFORMS
V CC
7.0V
VIN
Pulse
Generator
VOUT
500Ω
D.U.T.
50pF
500Ω
RT CL
INDUSTRwIAwLwT.EDMaPtaESRhAeeTtU4RU.EcRomANGE
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
Propagation Delay
Test Circuits for All Outputs
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
VCC
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
tSU tH
tREM
SYNCHRONOUS
CONTROL
tSU tH
Set-up, Hold, and Release Times
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
1 MHz
Signal
Generator
Enable/Select(1)
Switch In
Switch In
(MUX) (2)
Switch
D.U.T. Out
VOUT (3)
CL =
50pF
Charge Injection
NOTES:
1. Select is used with multiplexers for measuring IQDCII during multiplexer select. During
all other tests Enable is used.
2. Used with multiplexers to measure IQDCII only.
3. Charge Injection = ∆VOUT CL, with Enable toggling for IQCII or Select toggling for IQDCII.
∆VOUT is the change in VOUT and is measured with a 10MΩ probe.
LOW-HIGH-LOW
PULSE
1.5V
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
tW
HIGH-LOW-HIGH
PULSE
1.5V
Pulse Width
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74FST163211.PDF ] | |
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