ZL2005P Datasheet PDF - Intersil Corporation
| Part Number | ZL2005P | |
| Description | Digital-DC Controller | |
| Manufacturers | Intersil Corporation | |
| Logo |  |
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Data Sheet
ZL2005P
www.DataSheet4U.com
February 18, 2009
FN6849.0
Digital-DC™ Controller with Drivers and POLA/DOSA Trim
Description
The ZL2005P is an innovative mixed-signal power
conversion and management IC that combines a com-
pact, efficient, synchronous DC-DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple low-voltage power
domains on a single PCB.
The ZL2005P is designed to be configured either as a
standard ZL2005 or as POLA/DOSA compatible
device.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005P uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
Features Power Conversion
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.54 V to 5.5 V output range (with margin)
• Optional output voltage setting with VADJ pin
• ± 1% output accuracy
• Internal 3 A drivers support >40 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I2C/SMBus communication
• Output overvoltage and overcurrent protection
• Internal non-voltatile memory (NVM)
• PMBus compliant
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
SS (0,1)
VTRK
MGN
SYNC
VADJ
SCL
SDA
SALRT
POWER
MANAGEMENT
LDO
NON-
VOLATILE
MEMORY
I2C
DRIVER
PWM
CONTROLLER
MONITOR
ADC
CURRENT
SENSE
TEMP
SENSOR
BST
GH
SW
GL
ISENA
ISENB
SA (0,1)
XTEMP VSEN
PGND SGND DGND
Figure 1. Block Diagram
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
|
| |
 
ZL2005P
Table 3. Electrical Specifications
www.DataSheet4U.com
Unless otherwise specified VDD = 12 V, TA = -40oC to +85oC. Typical values are at TA = 25oC. (Continued)
Parameter
Condition
Min Typ Max Unit
Soft start ramp duration range
Configurable via I2C/SMBus
0
– 200 ms
Soft start ramp duration accuracy
– 100 – µs
Logic Input/Output Characteristics
Logic input bias current
EN, PG, SCL, SDA, SALRT
-10
– 10 μA
Logic input low threshold (VIL)
Logic input OPEN (N/C)
Multi-mode logic pins
Logic input high threshold (VIH)
Logic output low (VOL)
IOL <= 4 mA
Logic output high (VOH)
IOH >= - 2 mA
Oscillator and Switching Characteristics
– – 0.8 V
– 1.4 – V
2 – –V
– – 0.4 V
2.25 – – V
Switching frequency range
200 – 1400 kHz
Switching frequency setpoint
accuracy
Predefined settings
(See table 13)
-5 – 5 %
Maximum PWM duty cycle
Factory default
95 – – %
Minimum SYNC pulse width
150 – – ns
Input clock frequency drift tolerance
Gate Drivers
External clock signal
-13 – 13 %
High-side driver voltage
(VBST - VSW)
High-side driver peak gate drive
current (pull down)
(VBST - VSW) = 4.5 V
– 4.5 – V
2 3 –A
High-side driver pull-up resistance
High-side driver pull-down
resistance
Low-side driver peak gate drive
current (pull-up)
(VBST - VSW) = 4.5 V,
(VBST - VGH) = 50 mV
(VBST - VSW) = 4.5 V,
(VGH - VSW) = 50 mV
VR = 5 V
– 0.8 2 Ω
– 0.5 2 Ω
– 2.5 – A
Low-side driver peak gate drive
current (pull-down)
VR = 5 V
– 1.8 – A
Low-side driver pull-up resistance
Low-side driver pull-down
resistance
Switching timing
VR = 5 V,
(VR - VGL) = 50 mV
VR = 5 V,
(VGL - PGND) = 50 mV
– 1.2 2 Ω
– 0.5 2 Ω
GH rise and fall time
GL rise and fall time
Tracking
(VBST - VSW) = 4.5 V,
CLOAD = 2.2 nF
VR = 5 V,
CLOAD = 2.2 nF
– 5 20 ns
– 5 20 ns
VTRK input bias current
VTRK = 5.5 V
– 110 200 µA
VTRK tracking threshold
VTRK >= 0.3 V
– 100
100 mV
5 FN6849.0
February 18, 2009
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ZL2005P electronic component. |
| Information | Total 30 Pages | |
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| Download | [ ZL2005P.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
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