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PDF MAX13326 Data sheet ( Hoja de datos )
| Número de pieza | MAX13326 | |
| Descripción | Dual Automotive Audio Line Drivers | |
| Fabricantes | Maxim Integrated Products | |
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19-5136; Rev 0; 1/10
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
General Description
The MAX13325/MAX13326 dual audio line drivers provide
a reliable differential interface between automotive audio
components. The devices feature differential inputs and
outputs, integrated output diagnostics, and are controlled
using an I2C interface or operate in stand-alone mode.
The outputs can deliver up to 4VRMS into 100I loads.
The MAX13325 buffers analog audio signals for trans-
mission over long cable distances with a fixed gain of
12dB, whereas the MAX13326 provides a 0dB fixed
gain. The diagnostics on the outputs report conditions
on a per channel basis, including short to GND, short
to battery, overcurrent, overtemperature, and excessive
offset. The output amplifiers can drive capacitive loads
up to 4nF to ground and 3nF differentially.
The outputs are protected according to IEC 61000-4-2
Q8kV Contact Discharge, and Q15kV Air Gap. The
MAX13325/MAX13326 are specified from -40NC to
+105NC and are available in a 28-pin TSSOP package
with an exposed pad.
Applications
Automotive Radio and Rear Seat Entertainment
Professional Remote Audio Amplifiers
Typical Operating Circuit
C6
100nF
TO
MICROPROCESSOR
FROM AUDIO
SOURCE
FROM AUDIO
SOURCE
C7
2.2µF
C8
2.2µF
C9
2.2µF
C10
2.2µF
ADD1
ADD0
SDA
SCL
FLAG
SHDN
MUTE
+5V
VL
I2C INTERFACE
AND
DIGITAL CONTROL
C1
470nF
C2
1µF
CP CM CHOLD
CHARGE
PUMP
BIAS
* OPTIONAL
R1
1kI
D1
VDD
PGND
+12V
Q1
C3
1µF
C4
BIAS 10µF
C5
CSS 220nF
GND
INLP
LEFT
INLM
OUTLP
1nF
OUTLM
TO
TRANSMISSION
LINE
INRP
INRM
RIGHT
OUTPUT
ESD
DIAGNOSTIC PROTECTION
OUTRP
OUTRM 1nF
TO
TRANSMISSION
LINE
MAX13325
MAX13326
*OPTIONAL : NEEDED FOR AUTOMOTIVE LOAD DUMP PROTECTION ONLY
Features
S Comprehensive Programmability and Diagnostics
Using I2C Interface
S Autoretry Function in Stand-Alone Mode
S Drive Capacitive Loads ≤ 3nF Differentially, ≤ 4nF
to Ground
S 112dB Signal-to-Noise Ratio
S Low 0.002% THD at 4VRMS into 2.7kI Loads
S High PSRR (70dB at 1kHz)
S High CMRR (80dB at 1kHz)
S Low Output Noise (3µVRMS), MAX13326
S Excellent Channel-to-Channel Matching
S Load-Dump Transient Protection
S Protected Output Against Various Short-Circuit
Conditions
S ESD Protection for ±8kV Contact Discharge,
±15kV Air Gap
S Long-Distance Drive Capability Typically Up to
15m or Greater
S Noise-Rejecting Differential Inputs and Outputs
S Low-Power Shutdown Mode < 10µA
S Hardware or Software MUTE Function
S 28-Pin TSSOP Package with Exposed Pad
Ordering Information
PART
PIN-
PACKAGE
TEMP
RANGE
MAX13325GUI/V+ 28 TSSOP-EP*
-40NC to
+105NC
MAX13326GUI/V+** 28 TSSOP-EP*
-40NC to
+105NC
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
GAIN
(dB)
12
0
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
DIGITAL CHARACTERISTICS
(VDD = 14.4V, VL = 3.3V, TA = TJ = -40NC to +105NC, typical values are TA = +25NC, unless otherwise noted.) (Note 2)
PARAMETER
DIGITAL INTERFACE
Input-Voltage High
Input-Voltage Low
Input-Voltage Hysteresis
Input Leakage Current
Output Low Voltage
Output Leakage Current
Stand-Alone FLAG Pulse Width
Stand-Alone Fault Retry Time
I2C TIMING
Serial-Clock Frequency
Bus Free Time
Hold Time
SCL Low Time
SCL High Time
Data Hold Time
Data Setup Time
Bus Capacitance
Receiving Rise Time
Receiving Fall Time
Transmitting Fall Time
STOP Condition Setup Time
Pulse Width of Suppressed Spike
SYMBOL
VINH
VINL
fSCL
tBUF
tHD,STA
tLOW
tHIGH
tHD:DAT
tSU:DAT
CB
tR
tF
tF
tSU:STO
tSP
CONDITIONS
VL = 2.7V to 5.5V
VL = 2.7V to 5.5V
MIN
0.75 x VL
FLAG, SDA, ISINK = 3mA
FLAG, SDA = 5.5V
ADD0, ADD1 = GND
ADD0, ADD1 = GND
0
Between START and STOP conditions
1.3
Repeated START condition
0.6
1.3
0.6
0
100
Per bus line
SCL, SDA
20 + 0.1CB
SCL, SDA
20 + 0.1CB
SDA, VL = 3.6V
20 + 0.05CB
0.6
0
TYP
50
100
500
MAX UNITS
0.25 x VL
Q100
0.4
2
V
V
mV
FA
V
FA
ms
ms
400 kHz
Fs
Fs
Fs
Fs
900 ns
ns
400 pF
300 ns
300 ns
250 ns
Fs
50 ns
Note 2: All devices are 100% tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note
Note
3:
3:
Signal
Signal
path
Path
gain is
Gain is
defined
defined
as:
as
20
×
log
(VOUT_ + )
(VIN_ +)
− (VOUT_−)
− (VIN_− )
.
Note 4: Measured in differential output mode, differential input voltage 4VP-P (for 0dB gain), 1VP-P (for 12dB gain) 1kHz:
Common-mode output balance is defined as
Common-Mode Output Balance is defined as
20
×
log
(
(| VOUT_+ )
VOUT_ + ) +
− ( VOUT_− )
( VOUT_− ) ×
2
.
Note 5: Measurement bandwidth 22Hz to 22kHz.
Note 6: KCP level is calculated as 20log[(peak voltage during mode transition, no input signal)/1VRMS]. Units are expressed in
dBV.
_______________________________________________________________________________________ 5
5 Page 
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Dual Automotive, Audio Line Drivers
with I2C Control and Diagnostic
Left-Channel Faults
Table 5. Left-Channel Fault Register Format
FUNCTION
ADDRESS
CODE
(HEX)
D7
REGISTER DATA
D6 D5 D4 D3
POR STATE
D2 D1 D0 (HEX)
Left-Channel
Fault Register
0x03
SVDDL SGNDL LIMITL
x OFFSETL OPENL
x
x
0x00
SVDDL: The SVDDL bit is set to ‘1’ when a short to VDD is detected on the left channel.
SGNDL: The SGNDL bit is set to ‘1’ when a short to GND is detected on the left channel.
LIMITL: The LIMITL bit is set to ‘1’ when the current-limit threshold is tripped for left output.
OFFSETL: The OFFSETL bit is set to ‘1’ when excessive offset is detected on the left-channel output.
OPENL: The OPENL bit is set to ‘1’ when an open load is detected on the left channel.
Set the appropriate mask bit in the LMASK register to detect the faults on the left channel. See Table 9.
When any bit of the LFAULT register is high, the FLAG output is low.
Right-Channel Faults
Table 6. Right-Channel Fault Register Format
FUNCTION
ADDRESS
CODE
(HEX)
D7
REGISTER DATA
D6 D5 D4 D3
Right-Channel
Fault Register
0x04
SVDDR SGNDR LIMITR x
OFFSETR
D2
OPENR
D1
x
POR STATE
D0 (HEX)
x 0x00
SVDDR: The SVDDR bit is set to ‘1’ when a short to VDD is detected on the right channel.
SGNDR: The SGNDR bit is set to ‘1’ when a short to GND is detected on the right channel.
LIMITR: The LIMITR bit is set to ‘1’ when the current-limit threshold is tripped for right output.
OFFSETR: The OFFSETR bit is set to ‘1’ when excessive offset is detected on the right-channel output.
OPENR: The OPENR bit is set to ‘1’ when an open load is detected on the right channel.
Set the appropriate mask bit in the RMASK register to detect the faults on the right channel. See Table 10.
When any bit of the RFAULT register is high, the FLAG output is pulled low.
Table 7. Flag Register Format
FLAG Register
FUNCTION
ADDRESS
CODE
(HEX)
D7
D6
REGISTER DATA
D5 D4 D3
POR STATE
D2 D1 D0
(HEX)
FLAG
Register
0x05
FLAG LHIGHZ RHIGHZ OFFSETL OFFSETR ID2 ID1 ID0 0x02/0x03
FLAG: FLAG bit is set to ‘1’ when the FLAG output is logic-low. The FLAG bit allows to quickly access the status of the
device without using the FLAG output and without having to read all the fault registers.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX13326.PDF ] | |
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