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PDF LTC6603 Data sheet ( Hoja de datos )
| Número de pieza | LTC6603 | |
| Descripción | Dual Adjustable Lowpass Filter | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Guaranteed Phase and Gain Matching Specs
n Programmable BW Up to 2.5MHz
n Programmable Gain (0dB/6dB/12dB/24dB)
n 9th Order Linear Phase Response
n Differential, Rail-to-Rail Inputs and Outputs
n Low Noise: –145dBm/Hz (Input Referred)
n Low Distortion: –75dBc at 200kHz
n Simple Pin Programming or SPI Interface
n Set the Max Speed/Power with an External R
n Operates from 2.7V to 3.6V
n Input Range from 0V to 5.5V
n 4mm × 4mm QFN Package
APPLICATIONS
n Small/Low Cost Basestations:
IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA,
UMTS
n Low Cost Repeaters, Radio Links, and Modems
n 802.11x Receivers
n JTRS
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC6603www.DataSheet4U.com
Dual Adjustable
Lowpass Filter
DESCRIPTION
The LTC®6603 is a dual, matched, programmable lowpass
filter for communications receivers and transmitters. The
selectivity of the LTC6603, combined with its linear phase,
phase matching and dynamic range, make it suitable for
filtering in many communications systems. With 1.5°
phase matching between channels, the LTC6603 can be
used in applications requiring pairs of matched filters,
such as transceiver I and Q channels. Furthermore, the
differential inputs and outputs provide a simple interface
for most communications systems.
The sampled data filter does not require an external clock
yet its cutoff frequency can be set with a single external
resistor with an accuracy of 3.5% or better. The external
resistor programs an internal oscillator whose frequency
is divided prior to being applied to the filter networks.
This allows up to three cutoff frequencies that can be
obtained for each external resistor value, allowing the
cutoff frequency to be programmed over a range of more
than six octaves. Alternatively, the cutoff frequency can
be set with an external clock. The filter gain can also be
programmed to 1, 2, 4 or 16.
The LTC6603 features a low power shutdown mode that
can be programmed through the serial interface and is
available in a 24-pin 4mm × 4mm QFN package.
TYPICAL APPLICATION
IIN
QIN
0.1μF
30.9k
0.1μF
BASEBAND
GAIN CONTROL
2.5MHz I and Q Lowpass Filter and Dual ADC
5V 3V
49.9Ω 100nH*
0.1μF
0.1μF
V+IN V+A V+D
+INA
–INA
+INB
–INB
RBIAS
+OUTA
–OUTA
+OUTB
LTC6603 –OUTB
CLKIO
VOCM
SER
I OUTPUT
49.9Ω 100nH*
49.9Ω 100nH*
Q OUTPUT
49.9Ω 100nH*
180pF
10pF
180pF
10pF
180pF
10pF
180pF
10pF
CAP
CLKCNTL
3V
VCM
LTC2297
14-BIT
ADC
14-BIT
ADC
GAIN1
GAIN0
GND
GND
SDO
SDI
LPFO
LPF1
3V
2.2μF
*COILCRAFT 0603HP
6603 TA01a
Phase Matching
60
VS = 3V, BW = 156.25kHz
f = 125kHz, TA = 25°C
50 1000 UNITS
40
30
20
10
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5
MISMATCH (DEG)
6603 TA01b
6603f
1
1 page  
w w LTwC.66D03a t a
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff =
2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted.
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
CLKIO Pin Low Level
Output Voltage
CLKIO Pin Rise Time
CLKIO Pin Fall Time
SER High Level
Input Voltage
SER Low Level
Input Voltage
SER Input Current
CLKCNTL High Level
Input Voltage
V+A = V+D = 3V, CLKCNTL = 3V
IOL = 1mA
IOL = 4mA
V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF
V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF
Pin 17
Pin 17
Pin 17 = 0V (Note 6)
Pin 17 = V+D
Pin 5
l V+D – 0.3
0.05
0.1
0.3
0.3
l
l –10
l
l V+D – 0.5
0.3
2
V
V
ns
ns
V
V
μA
μA
V
CLKCNTL Low Level Pin 5
Input Voltage
0.5 V
CLKCNTL Input
Current
CLKCNTL = 0V (Note 6)
CLKCNTL = V+D
l –25
–15
l 15 25
μA
μA
Pin Programmable Control Mode Specifications. Specifications apply to pins 6, 9, 21 and 22 in pin programmable control mode.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
V+D = 2.7V to 3.6V
VIH
Digital Input High Voltage
Pins 6, 9, 21, 22
l2
V
VIL
Digital Input Low Voltage
Pins 6, 9, 21, 22
l
0.8 V
IIN
Digital Input Current
Pins 6, 9, 21, 22 (Note 6)
l –1
1 μA
Serial Port DC and Timing Specifications. Specifications apply to pins 6, 9-11, and 21 in serial programming mode.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP
V+D = 2.7V to 3.6V
VIH
Digital Input High Voltage
Pins 6, 9, 10
l2
VIL
Digital Input Low Voltage
Pins 6, 9, 10
l
IIN
Digital Input Current
Pins 6, 9, 10 (Note 6)
l –1
VOH
Digital Output High Voltage
Pins 11, 21 Sourcing 500μA
l VSUPPLY – 0.3
VOL
Digital Output Low Voltage
Pins 11, 21 Sinking 500μA
l
t1 (Note 5)
SDI Valid to SCLK Setup
l 60
t2 (Note 5)
SDI Valid to SCLK Hold
l0
t3 SCLK Low
l 100
t4
t5
t6 (Note 5)
t7 (Note 5)
SCLK High
CS Pulse Width
LSB SCLK to CS
CS Low to SCLK
l 100
l 60
l 60
l 30
t8
t9 (Note 5)
SDO Output Delay
SCLK Low to CS Low
CL = 15pF
l
l0
MAX UNITS
V
0.8 V
1 μA
V
0.3 V
ns
ns
ns
ns
ns
ns
ns
125 ns
ns
6603f
5
5 Page 
LTC6603www.DataSheet4U.com
PIN FUNCTIONS
LPF1(CS) (Pin 6): TTL Level Input. When in pin program-
mable control mode, this pin is the MSB of the lowpass
cutoff frequency control code; in serial control mode, this
pin is the chip select input (active low).
+INB, –INB (Pins 7, 8): Channel B differential inputs.
The input range and input resistance are described in the
Applications Information section. Input voltages which
exceed V+IN (Pin 1) should be avoided.
LPF0(SCLK) (Pin 9): TTL Level Input. When in pin program-
mable control mode, this pin is the LSB of the lowpass
cutoff frequency control code; in serial control mode, this
pin is the clock of the serial interface.
SDI (Pin 10): TTL Level Input. When in pin programmable
control mode, this pin is left floating; in serial control
mode, this pin is the serial data input.
SDO (Pin 11): TTL Level Input. When in pin programmable
control mode, this pin is left floating; in serial control
mode, this pin is the serial data output.
–OUTB, +OUTB (Pins 12, 13): Channel B differential filter
outputs. These pins can drive 1k and/or 50pF loads. For
larger capacitive loads, an external 100Ω series resistor
is recommended for each output. The common mode
voltage of the filter outputs is the same as the voltage at
VOCM (Pin 3).
GND (Pin 14): Ground. Should be tied to a ground plane
for best performance.
CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground,
CLKIO is the master clock input. When CLKCNTL is floated,
CLKIO is pulled to ground by a weak pulldown. When
CLKCNTL is tied to V+D (Pin 16), CLKIO is the master
clock output. When configured as a clock output, this pin
can drive 1k and/or 5pF loads (heavier loads will cause
inaccuracies).
V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V).
This supply must be kept free from noise and ripple. It
should be bypassed directly to a ground plane with a 0.1μF
capacitor. The bypass should be as close as possible to
the IC.
SER (Pin 17): Interface Selection Input. When tied to V+D
(Pin 16) or floated, the interface is in pin programmable
control mode, i.e. the filter gain and cutoff frequencies
are programmed by the GAIN1, GAIN0, LPF1 and LPF0
pins. When SER is tied to ground, the filter gain, the filter
cutoff frequency and shutdown mode are programmed
by the serial interface.
–OUTA, +OUTA (Pins 18, 19): Channel A differential filter
outputs. These pins can drive 1k and/or 50pF loads. For
larger capacitive loads, an external 100Ω series resistor
is recommended for each output. The common mode
voltage of the filter outputs is the same as the voltage at
VOCM (Pin 3).
CAP (Pin 20): Connect a 0.1μF bypass capacitor to this
pin. Pin 20 is a buffered version of Pin 3.
GAIN0(D0) (Pin 21): TTL Level Input. When in pin pro-
grammable control mode, this pin is the LSB of the gain
control code; in serial control mode, this pin is the LSB
of the serial control register, an output.
GAIN1 (Pin 22): TTL Level Input. When in pin programmable
control mode, this pin is the MSB of the gain control code;
in serial control mode, this pin is a no-connect.
–INA, +INA (Pins 23, 24): Channel A differential inputs.
The input range and input resistance are described in the
Applications Information section. Input voltages which
exceed V+IN (Pin 1) should be avoided.
Exposed Pad (Pin 25): Ground. The Exposed Pad must
be soldered to PCB.
6603f
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC6603.PDF ] | |
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