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PDF ADL5801 Data sheet ( Hoja de datos )
| Número de pieza | ADL5801 | |
| Descripción | High IP3 10 MHz to 6 GHz Active Mixer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Broadband upconverter/downconverter
Power conversion gain of 1.8 dB
Broadband RF, LO, and IF ports
SSB noise figure (NF) of 9.75 dB
Input IP3: 28.5 dBm
Input P1dB: 13.3 dBm
Typical LO drive: 0 dBm
Single-supply operation: 5 V at 130 mA
Adjustable bias for low power operation
Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
APPLICATIONS
Cellular base station receivers
Radio link downconverters
Broadband block conversion
Instrumentation
GENERAL DESCRIPTION
The ADL5801 uses a high linearity, doubly balanced, active
mixer core with integrated LO buffer amplifier to provide high
dynamic range frequency conversion from 10 MHz to 6 GHz.
The mixer benefits from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. An optional input power detector is provided for
adaptive bias control. The high input linearity allows the device
to be used in demanding cellular applications where in-band
blocking signals may otherwise result in degradation in
dynamic performance. The adaptive bias feature allows the part
to provide high input IP3 performance when presented with
large blocking signals. When blockers are removed, the
ADL5801 can automatically bias down to provide low noise
figure and low power consumption.
High IP3,www.DataSheet4U.com
10 MHz to 6 GHz, Active Mixer
ADL5801
FUNCTIONAL BLOCK DIAGRAM
VPLO GND NC IFON IFOP GND
24 23 22 21 20 19
GND 1 ADL5801
GND 2
LOIP 3
LOIN 4
GND 5
GND 6
V2I
DET
18 VPRF
17 GND
16 RFIP
15 RFIN
14 GND
13 VPDT
7 8 9 10 11 12
VPLO GND ENBL VSET DETO GND
Figure 1.
The balanced active mixer arrangement provides superb LO-to-
RF and LO-to-IF leakage, typically better than −40 dBm. The IF
outputs are designed to provide a typical voltage conversion
gain of 7.8 dB when loaded into a 200 Ω load. The broad
frequency range of the open-collector IF outputs allows the
ADL5801 to be applied as an upconverter for various transmit
applications.
The ADL5801 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm × 4 mm,
24-lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
GND 2
LOIP 3
LOIN 4
GND 5
GND 6
PIN 1
INDICATOR
ADL5801
TOP VIEW
(Not to Scale)
18 VPRF
17 GND
16 RFIP
15 RFIN
14 GND
13 VPDT
ADL5801
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NOTES
1. THERE IS AN EXPOSED PADDLE THAT
MUST BE SOLDERED TO GROUND.
2. NC = NO CONNECT.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 5, 6, 8, 12, GND
14, 17, 19, 23
Device Common (DC Ground).
3, 4
LOIP, LOIN
Differential LO Input Terminal. Internally matched to 50 Ω. Must be ac-coupled.
7, 24
VPLO
Positive Supply Voltage for LO System.
9
ENBL
Device Enable. Pull high to disable the device; pull low to enable.
10
VSET
Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core
and allows for adaptive control of the input IP3 and NF characteristics of the mixer core.
11
DETO
Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is
proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin,
the part auto biases and increases input IP3 performance when presented with large signal input levels.
13
VPDT
Positive Supply Voltage for Detector.
15, 16
RFIN, RFIP
Differential RF Input Terminal. Internally matched to 50 Ω differential input impedance. Must be
ac-coupled.
18
VPRF
Positive Supply Voltage for RF Input System.
20, 21
IFOP, IFON
Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap
of the IF transformer.
22 NC Not Connected.
EPAD
The exposed paddle must be soldered to ground.
Rev. 0 | Page 5 of 20
5 Page 
CIRCUIT DESCRIPTION
The ADL5801 includes a double-balanced active mixer with a
50 Ω input impedance and 250 Ω output impedance. In addition,
the ADL5801 integrates a local oscillator (LO) amplifier and
an RF power detector that can be used to optimize the mixer
dynamic range. The RF and LO are differential, providing max-
imum usable bandwidth at the input and output ports. The LO
also operates with a 50 Ω input impedance and can, optionally,
be operated differentially or single ended. The input, output, and
LO ports can be operated over an exceptionally wide frequency
range. The ADL5801 can be configured as a downconvert mixer
or as an upconvert mixer.
The ADL5801 can be divided into the following sections: the
LO amplifier and splitter, the RF voltage-to-current (V-to-I)
converter, the mixer core, the output loads, the RF detector, and
the bias circuit. A simplified block diagram of the device is
shown in Figure 27. The LO block generates a pair of
differential LO signals to drive two mixer cores. The RF input
power is converted into RF currents by the V-to-I converter that
then feed into the two-mixer core. The internal differential load
of the mixer provides a wideband 250 Ω output impedance from
the mixer. Reference currents to each section are generated by
the bias circuit, which can be enabled or disabled using the ENBL
pin. A detailed description of each section of the ADL5801
follows.
VPLO GND NC IFON IFOP GND
24 23 22 21 20 19
GND 1 ADL5801
GND 2
LOIP 3
LOIN 4
GND 5
GND 6
V2I
DET
18 VPRF
17 GND
16 RFIP
15 RFIN
14 GND
13 VPDT
7 8 9 10 11 12
VPLO GND ENBL VSET DETO GND
Figure 27. Block Diagram
LO AMPLIFIER AND SPLITTER
The LO input is conditioned by a series of amplifiers to provide
a well controlled and limited LO swing to the mixer core, result-
ing in excellent input IP3. The LO input is amplified using a
broadband low noise amplifier (LNA) and is then followed by
LO limiting amplifiers. The LNA input impedance is nominally
50 Ω. The LO circuit exhibits low additive noise, resulting in an
excellent mixer noise figure and output noise under RF
blocking. For optimal performance, the LO inputs should be
driven differentially but at lower frequencies; single-ended drive
is acceptable.
ADL5801
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RF VOLTAGE-TO-CURRENT (V-TO-I) CONVERTER
The differential RF input signal is applied to a V-to-I converter
that converts the differential input voltage to output currents.
The V-to-I converter provides a 50 Ω input impedance. The V-to-
I section bias current can be adjusted up or down using the
VSET pin. Adjusting the current up improves IP3 and P1dB
input but degrades the SSB noise figure. Adjusting the current
down improves the SSB noise figure but degrades IP3 and P1dB
input. Conversion gain remains nearly constant over a wide
range of VSET pin settings, allowing the part to be adjusted
dynamically without affecting conversion gain. The current
adjustment can be made by connecting a resistor from the
VSET pin to the positive supply to increase the bias current or
from the VSET pin to ground to decrease the bias current.
Optionally, the VSET pin can be connected to the DETO pin to
provide automatic setting of the mixer core current.
MIXER CORE
The ADL5801 has a double-balanced mixer that uses high per-
formance SiGe NPN transistors. This mixer is based on the
Gilbert cell design of four cross-connected transistors.
MIXER OUTPUT LOAD
The mixer load uses a pair of 125 Ω resistors connected to the
positive supply. This provides a 250 Ω differential output resis-
tance. The mixer output should be pulled to the positive supply
externally using a pair of RF chokes or using an output trans-
former with the center tap connected to the positive supply. It
is possible to exclude these components when the mixer core
current is low, but both P1dB input and IP3 input are then
reduced.
The mixer load output can operate from direct current (dc) up
to approximately 600 MHz into a 200 Ω load. For upconversion
applications, the mixer load can be matched using off-chip
matching components. Transmit operation up to 2 GHz is
possible. See the Applications Information section for matching
circuit details.
RF DETECTOR
An RF power detector is buffered from the V-to-I converter
section. This detector has a power response range from
approximately −25 dBm up to 0 dBm and provides a current
output. The output current is designed to be connected to the
VSET pin to boost the mixer core current when large RF signals
are present at the mixer input. An external capacitor can be
used to adjust the response time of this function. If not used,
the DETO pin can be left open or connected to ground.
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADL5801.PDF ] | |
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