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PDF LC72714W Data sheet ( Hoja de datos )
| Número de pieza | LC72714W | |
| Descripción | Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : ENN6871A
CMOS IC
LC72714W
Mobile FM Multiplex Broadcast IC
with On-Chip VICS Decoder
Overview
The LC72714W is data demodulator ICs for receiving FM
multiplex broadcasts for mobile reception in the DARC
format. This IC includes an on-chip bandpass filter for
extracting the DARC signal from the FM baseband signal.
It also integrates a decoder circuit that performs the VICS
data processing on the same chip and can implement a
compact, multifunction VICS reception system. The
LC72714W is an improved version of the LC72710W that
features circuit improvements that allow a single tuner to
receive both the VICS data and the dGPS data supported
by the earlier device. Note that a contract with VICS
Center is required to evaluate this sample IC and to
produce end products that support VICS.
Functions
• Adjustment-free 76 kHz SCF bandpass filter
• Built-in VICS decoder
• MSK delay detection system based on a 1T delay.
• Error correction function based on a 2T delay (in the
MSK detection stage)
• Digital PLL based clock regeneration function
• Shift-register 1T and 2T delay circuits
• Block and frame synchronization detection circuits
• Functions for setting the number of allowable BIC errors
and the number of synchronization protection
operations.
• Error correction using (272, 190) codes
• Built-in layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for
vertical correction
• 7.2 MHz crystal oscillator circuit
• Two power saving modes: STNBY and EC STOP
• Dedicated frame synchronization circuit for
simultaneous reception of dGPS and VICS data
• Applications can use either a parallel CPU interface
(DMA) or a CCB serial interface.
• Supply voltage: 2.7 to 3.6 V
Package Dimensions
unit: mm
3190-SQFP64
[LC72714W]
12.0
10.0
1.25 0.5 0.18
48
49
1.25
33
32
0.15
64
1
17
16
0.5 0.5
SANYO: SQFP64
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92001TN (OT) No. 6871-1/29
1 page  
LC72714W
Pin Functions
Pin No.
3
4
13
38
39
40
41
42
43
44
46
45
Pin
IOCNT1
IOCNT2
DACK
WR
RD
A0/CL
A1/CE
A2/DI
A3
CS
RST
STNBY
47 SP
48 BUSWD
60 TEST
58 TPC1
59 TPC2
61 TOSEL1
62 TOSEL2
49 TIN
5 CLK16
6 DATA
9 FCK
10 BCK
7 FLOCK
8 BLOCK
11 CRC4
33 INT
12 DREQ
16 RDY
17 to 24 D0 to D7
Function
Data bus I/O control 1 (SP = low)*1
Data bus I/O control 2 (SP = low)*1
DMA acknowledge (SP = low)*1
Write control signal (SP = low)*1
Read control signal (SP = low)*1
Address input 0 (SP = low) CCB CL input (SP = low)
1 (SP = low) CCB CE input (SP = low)
2 (SP = low) CCB DI input (SP = low)
3 (SP = low)*1
Chip select input (SP = L)*1
System reset input (negative logic)
Standby mode (positive logic)
I/O
Input
SP = low: parallel, SP = high: serial
BUSWD = low: 8 bits, BUSWD = high: 16 bits
The test pin must be connected to the digital system ground (VSS).
Must be connected to the digital system power supply (VDD) or ground
(VSS) in normal operation.
As above
As above
As above
As above
Input
Clock regeneration monitor
Demodulated data monitor
Frame start signal output
Block start signal output
Outputs a high level during frame synchronization
Outputs a high level during block synchronization
Level 4 CRC detection result output
External CPU interrupt request output
DMA request signal
Read ready signal
Output
Data bus
The bus width can be set to be either 8 bits or 16 bits by the BUSWD
pin (pin 48).
For data input, only the lower 8 bits (D0 to D7) are valid. *3
I/O
25 to 32
D8 to D15
Data bus (in 16-bit mode)
These pins are held in the output off state when BUSWD is low.
Output
64 XIN Connections for the system clock crystal oscillator circuit.
1
XOUT
The XIN pin can also be used as an external clock signal input.
I/O
53
MPXIN
Baseband (multiplex) signal input
Input
55
FLOUT
Subcarrier output (76 kHz bandpass filter output)
Output
Pin circuit
+
–
Continued on next page.
No. 6871-5/29
5 Page 
LC72714W
Data Update Timing for Read Registers
The data in the two read registers (the status register at address 01H and the block number register at address 02H) is
updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point
immediately before the INT output.
In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will
be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that
data. For example, if error correction failed and the erroneous data is not required, the application should simply wait for
the next interrupt.
If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from the
additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout.
Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application
checks the current reception status by reading out the status register and checking bit 6 (data received in the block
synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7 (VH)
is 0 provides superior real time characteristics.
CPU Interface Timing <Parallel Mode>
• Register Read Timing
tWRDL1, tWRDL2
tCYRD
A0 to A3
CS
RD
RDY
tSARD
DATn
tHARD
tDRDY
tWRDY
tRDH
Valid
output
* tHARD stipulates the earliest timing for A0 to A3 and CS.
No. 6871-11/29
11 Page | ||
| Páginas | Total 29 Páginas | |
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