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PDF HYMD512M646BFS8-H Data sheet ( Hoja de datos )
| Número de pieza | HYMD512M646BFS8-H | |
| Descripción | Unbuffered DDR SO-DIMM | |
| Fabricantes | Hynix Semiconductor | |
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128Mx64 bits
Unbuffered DDR SO-DIMM
HYMD512M646B(L)FS8-J/M/K/H/L
Document Title
128Mx64 bits Unbuffered DDR SO-DIMM
Revision History
No.
History
Draft Date
Remark
0.1 Initial Draft
Jan. 2004
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Jan. 2004
1
1 page  
ABSOLUTE MAXIMUM RATINGS
www.DataSheet4U.com
HYMD512M646B(L)FS8-J/M/K/H/L
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
8
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
Unit
oC
oC
V
V
V
mA
W
oC / Sec
DC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol Min Typ.
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
VDD
VDDQ
VIH
VIL
VTT
VREF
2.3
2.3
VREF + 0.15
-0.3
VREF - 0.04
1.15
2.5
2.5
-
-
VREF
1.25
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
Max
2.7
2.7
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
1.35
Unit
V
V
V
V
V
V
Note
1
2
3
AC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.1 / Jan. 2004
5
5 Page 
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HYMD512M646B(L)FS8-J/M/K/H/L
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
- continued -
Parameter
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
Symbol
tDQSL
tDQSS
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSC
tREFI
DDR333
Min Max
0.35 -
0.75 1.25
0.45 -
0.45 -
1.75 -
0.9 1.1
0.4 0.6
0-
0.25 -
0.4 0.6
2-
200 -
- 7.8
DDR266(2-2-2)
Min Max
0.35 -
0.72 1.28
0.5 -
0.5 -
1.75 -
0.9 1.1
0.4 0.6
0-
0.25 -
0.4 0.6
2-
200 -
- 7.8
Unit Note
CK
CK
ns 6,7, 11~13
ns 6,7, 11~13
ns
CK
CK
CK
CK
CK
CK
CK 8
us
Rev. 0.1 / Jan. 2004
11
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