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PDF HYMD512M646AFS8-D4 Data sheet ( Hoja de datos )
| Número de pieza | HYMD512M646AFS8-D4 | |
| Descripción | Unbuffered DDR SO-DIMM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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128Mx64 bits
Unbuffered DDR SO-DIMM
HYMD512M646A(L)FS8-D43/D4
Document Title
128Mx64 bits Unbuffered DDR SO-DIMM
Revision History
No. History
0.1 Initial Draft
0.2
1) Reflected a “notational” change in module thickness on page 14 - Not Real ! -
2) Corrected some typos
Draft Date
Dec. 2003
Apr. 2004
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004
1
1 page  
ABSOLUTE MAXIMUM RATINGS
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HYMD512M646A(L)FS8-D43/D4
Parameter
Operating Temperature (Ambient)
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Rating
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
1.0 x # of Components
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
Unit
oC
oC
V
V
V
mA
W
oC / Sec
DC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol Min Typ. Max Unit Note
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
VDD
VDDQ
VIH
VIL
VTT
VREF
2.5
2.5
VREF + 0.15
-0.3
VREF - 0.04
0.49*VDDQ
2.6
2.6
-
-
VREF
0.5*VDDQ
2.7
2.7
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
V
V
V
V
V
V
1
2
3
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on VREF may not exceed +/- 2% of the DC value.
AC OPERATING CONDITIONS (TA= 0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2 / Apr. 2004
5
5 Page 
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HYMD512M646A(L)FS8-D43/D4
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400 (D43)
Min Max
Input Pulse Width
tIPW
2.2
-
Write DQS High Level Width
tDQSH
0.35
-
Write DQS Low Level Width
tDQSL
0.35
-
Clock to First Rising edge of DQS-In
tDQSS
0.72
1.28
DQS falling edge to CK setup time
tDSS
0.2
DQS falling edge hold time from CK
tDSH
0.2
Data-In Setup Time to DQS-In (DQ & DM)
tDS 0.4
-
Data-in Hold Time to DQS-In (DQ & DM)
tDH 0.4
-
DQ & DM Input Pulse Width
tDIPW
1.75
-
Read DQS Preamble Time
tRPRE
0.9
1.1
Read DQS Postamble Time
tRPST
0.4
0.6
Write DQS Preamble Setup Time
tWPRES
0
-
Write DQS Preamble Hold Time
tWPREH
0.25
-
Write DQS Postamble Time
Mode Register Set Delay
tWPST
tMRD
0.4
2
0.6
-
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
tXSC
tREFI
200
-
-
7.8
DDR400 (D4)
Min Max
2.2 -
0.35 -
0.35 -
0.72 1.28
0.2
0.2
0.4 -
0.4 -
1.75 -
0.9 1.1
0.4 0.6
0-
0.25 -
0.4 0.6
2-
200 -
- 7.8
- continued -
Unit Note
ns 6
CK
CK
CK
CK
CK
ns 6,7,11
,
ns 12,13
ns 6
CK
CK
CK
CK
CK
CK
CK 8
us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold
5. Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps ps
0.5 0 0
0.4 +50 0
0.3
+100
0
6. CK, /CK slew rates are >=1.0V/ns
7. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
Rev. 0.2 / Apr. 2004
11
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