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PDF HYMD512G726AK8M-H Data sheet ( Hoja de datos )
| Número de pieza | HYMD512G726AK8M-H | |
| Descripción | Low Profile Registered DDR SDRAM DIMM | |
| Fabricantes | Hynix Semiconductor | |
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Low Profile Registered DDR SDRAM DIMM
HYMD512G726A(L)8M-M/K/H/L
DESCRIPTION
Preliminary
Hynix HYMD512G726A(L)8M-M/K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAM
Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix
HYMD512G726A(L)8M-M/K/H/L series consists of eighteen 64Mx8 DDR SDRAM in 400mil TSOP II packages on a
184pin glass-epoxy substrate. Hynix HYMD512G726A(L)8M-M/K/H/L series provide a high performance 8-byte inter-
face in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD512G726A(L)8M-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD512G726A(L)8M-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect func-
tion is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to
identify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 1GB (128M x 72) Low Profile Registered DDR DIMM • Fully differential clock operations (CK & /CK) with
based on 64Mx8 DDR SDRAM
125MHz/133MHz
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Error Check Correction (ECC) Capability
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Registered inputs with one-clock delay
• tRAS Lock-out function supported
• Phase-lock loop (PLL) clock driver to reduce loading • Internal four bank operations with single pulsed RAS
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• Auto refresh and self refresh supported
• All inputs and outputs are compatible with SSTL_2
interface
• 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD512G726A(L)8M-M
HYMD512G726A(L)8M-K
HYMD512G726A(L)8M-H
HYMD512G726A(L)8M-L
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
133MHz (*DDR266 2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
125MHz (*DDR200)
Interface
Form Factor
SSTL_2
184pin Registered DIMM
5.25 x 1.2 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Jan. 2003
1
1 page  
www.DataSh
HYMD512G726A(L)8M-M/K/H/L
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (VIH, min)
AC Input Low Level Voltage (VIL, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (RT)
Series Resistor (RS)
Output Load Capacitance for Access Time Measurement (CL)
Value
VDDQ x 0.5
VDDQ x 0.5
VREF + 0.31
VREF - 0.31
VREF
VTT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
W
W
pF
Rev. 0.1/Jan. 2003
5
5 Page 
www.DataSheet4U.com
HYMD512G726A(L)8M-M/K/H/L
11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tDS
Delta tDH
V/ns
ps ps
0.5 0 0
0.4 +75 +75
0.3
+150
+150
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF
+/-310mV for a duration of up to 2ns.
I/O Input Level
Delta tDS
Delta tDH
mV ps ps
+280
+50 +50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS
slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns
and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
(1/SlewRate1)-(1/SlewRate2)
Delta tDS
Delta tDH
ns/V
ps ps
0 00
+/-0.25
+50 +50
+/- 0.5
+100
+100
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK
is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock
16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK2.
Rev. 0.1/Jan. 2003
11
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