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PDF LC72711LW Data sheet ( Hoja de datos )
| Número de pieza | LC72711LW | |
| Descripción | Mobile FM Multiplex Broadcast DARC Receiver IC | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Ordering number : ENN6167
CMOS IC
LC72711W, 72711LW
Mobile FM Multiplex Broadcast (DARC)
Receiver IC
Overview
The LC72711W and LC72711LW are data demodulator
ICs for receiving FM multiplex broadcasts for mobile
reception in the DARC format. This IC includes an on-
chip bandpass filter for extracting the DARC signal from
the FM baseband signal. Furthermore, since this IC
supports all of the IT-R recommended FM multiplex
frame structures (methods A, A', B, and C), it is optimal
for worldwide market radios that provide FM multiplex
reception. The LC72711W and LC72711LW support both
parallel and CCB serial CPU interfaces.
Functions
• Adjustment-free 76 kHz SCF bandpass filter
• Supports all FM multiplex frame structures (methods A,
A', B, and C) under CPU control.
• MSK delay detection system based on a 1T delay.
• Error correction function based on a 2T delay (in the
MSK detection stage)
• Digital PLL based clock regeneration function
• Shift-register 1T and 2T delay circuits
• Block and frame synchronization detection circuits
• Functions for setting the number of allowable BIC errors
and the number of synchronization protection
operations.
• Error correction using (272, 190) codes
• Built-in layer 4 CRC code checking circuit
• On-chip frame memory and memory control circuit for
vertical correction
• 7.2 MHz crystal oscillator circuit
• Two power saving modes: STNBY and EC_STOP
• Applications can use either a parallel CPU interface
(DMA) or a CCB serial interface.
• Supply voltage: 4.5 to 5.5 V (LC72711W), 2.7 to 3.6 V
(LC72711LW)
Package Dimensions
unit: mm
3190-SQFP64
[LC72711W, 72711LW]
12.0
10.0
1.25 0.5 0.18
48
49
1.25
33
32
0.15
64
1
17
16
0.5 0.5
SANYO: SQFP64
• CCB is a trademark of SANYO ELECTRIC CO., LTD.
• CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
12100RM (OT) No. 6167-1/29
1 page  
LC72711W, 72711LW
[LC72711LW]
Allowable Operating Ranges: Parallel Interface at Ta = –40 to +85°C, VSS = 0 V
Parameter
Address to RD setup
RD to address hold
RD low-level width
RD low-level width (when RDY is used)
RD cycle wait
RDY width (Register read)
RD data hold
Address to WR setup
WR to address hold
WR cycle wait
WR low-level width
WR data hold
RDY output delay
Corrected output RD width
Corrected output RD width
(when RDY is used)
RDY width (corrected output read)
DACK to DREQ delay
DMA cycle wait
RD low-level width (DMA)
Symbol
Conditions
tSARD
tHARD
tWRDL1
tWRDL2
tCYRD
tWRDY
tRDH
tSAWR
tHAWR
tCYWR
tWWRL
tWDH
tDRDY
tWDRD1
tWDRD2
tWDRDY
tDREQ
tCYDM
tWRDM
A0/CL, A1/CE, A2/DI, A3, RD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL→250 ns
RD
RD
A0/CL, A1/CE, A2/DI, A3, RD
RDY
RD, DATn
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
WR
WR, DATn
RD, RDY
RD (BUSWD = L 8 bits)
RD (BUSWD = H 16 bits)
RD (BUSWD = L 8 bits)
RD (BUSWD = H 16 bits)
RDY (BUSWD = L 8 bits)
RDY ((BUSWD = H 16 bits)
DREQ, DACK
RD, DREQ
RD
min
20
–20
280
100
150
60
0
20
20
150
200
0
0
300
540
100
300
60
300
300
Ratings
typ
max
280
230
50
300
540
230
490
260
420
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the “RD low-level width” will be 280 ns (minimum).
No. 6167-5/29
5 Page 
LC72711W, 72711LW
Control Registers
This IC includes both registers that can be read and registers that can be written. These registers can be accessed using
either the serial interface (CCB) or the parallel interface. The SP pin switches between these interfaces.
The initial values of the write registers are the data loaded into internal registers when a reset signal (RST) is received.
These values are recommended values that do not need to be changed during normal operation.
If the parallel interface is used, applications must hold the address fixed at 00H when reading out data to which error
correction has been applied. If the CCB interface is used, the application needs only to specify the CCB address (#FB).
The address 00H is an invalid address for writing.
The addresses other than those specified below are control addresses particular to the IC. Applications must not specify
those addresses.
Address
1
2
3
4
5
6
Register
Function
BIC Number of allowable BIC errors
SYNCB Block synchronization: error protection count
SYNCF Frame synchronization: error protection count
CTL1 Control register 1
CTL2 Control register 2
CRC4 Layer 4 CRC register
R/W
W
W
W
W
W
W
Address
1
2
Register
STAT
BLNO
Function
Status register
Block number register
R/W
R
R
Number of Allowable BIC Errors
Address Register R/W Initial value
01H BIC
W
22H
BIT7
BIT6
BIT5
Back protection
BIT4
(LSB)
BIT3
BIT2
BIT1
Forward protection
BIT0
(LSB)
The synchronization circuit in this IC operates by recognizing a 16-bit BIC code. The number of allowable errors is the
number of incorrect bits allowed in those 16 bits. This data sets up separate values for forward protection mode (when
synchronized) and for back protection mode (when not synchronized).
The default value is to allow 2 incorrect bits in both forward and back modes. If the block synchronization discrimination
output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we recommend setting the back
protection mode BIC allowable error count to 1 or 0.
Block Synchronization: Error Protection Count
Address Register R/W Initial value
02H SYNCB
W
17H
BIT7
BIT6
BIT5
Back protection
BIT4
(LSB)
BIT3
BIT2
BIT1
Forward protection
BIT0
(LSB)
The synchronization protection count can be set separately for both forward and back protection. The count conditions
for the protection counts are as follows.
• Back protection mode (not synchronized: BLOCK = low)
If the timing of the IC internal synchronization free-running counter matches the timing of the received BIC, the
protection count is incremented by 1. Contrarily, if the timings of the IC internal counter and the received BIC do not
match, the protection counter is cleared to 0. The timing of the count is the timing of the IC internal counter.
• Forward protection mode (synchronized: BLOCK = high)
In reverse to the back protection mode, if the timing of the IC internal free-running counter does not match the
detection timing of the received BIC, the protection counter is incremented, and if the timings match, the protection
counter is cleared to 0.
Figure 1 shows the states of the protection counter for the cases where the forward and back protection counts are both 3.
This IC defines the value of the protection counter to be 1 at the point that a match or a discrepancy between the IC
internal timing and the timing of the received BIC occurs. For example, when the value of the back protection count is 2,
the IC internal timing and the timing of the received BIC will have matched two times consecutively.
If the protection data is set to new values, for example if the protection counts are set to 3 as assumed in figure 1,
applications must send values which are 1 less than the intended value; in this case 22H. Similarly, if the value is set to
00H, the protection counts will, by definition, be set to 1 for both the forward and back directions. However, note that the
resulting operation will be equivalent to there being no protection circuit. The default values are 8 for the forward
protection count and 2 for the back protection count.
If the block synchronization output (BLOCK) is used for discriminating whether or not FM multiplex data is present, we
recommend setting the block synchronization back protection count to a value that is more strict than the default value.
(That is, we recommend replacing the default value of 2 with a value of 3 or higher.)
No. 6167-11/29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet LC72711LW.PDF ] | |
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