|
|
PDF HYMD512G726AM4-H Data sheet ( Hoja de datos )
| Número de pieza | HYMD512G726AM4-H | |
| Descripción | Registered DDR SDRAM DIMM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HYMD512G726AM4-H (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
|
No Preview Available !
Document Title
128M x 72 bits Registered DDR SDRAM DIMM
Revision History
No. History
0.1 1) Defined Target Spec.
1) Defined pin cap. spec.
0.2 2) Modified IDD current spec
3) Deleted preliminary.
www.DataSheet4U.com
128Mx72 bits
Registered DDR SDRAM DIMM
HYMD512G726A(L)4-M/K/H/L
Draft Date
Jan. 2003
Feb. 2004
Remark
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Feb. 2004
1
1 page  
www.DataSheet4U.com
HYMD512G726A(L)4-M/K/H/L
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature(ambient)
Storage Temperature
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
Symbol
TA
TSTG
VIN, VOUT
VDD
VDDQ
IOS
PD
TSOLDER
Rating
0 ~ +70
-55 ~ +125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
18
260 / 10
Note : Operation at above absolute maximum rating can adversely affect device reliability
Unit
oC
oC
V
V
V
mA
W
oC / Sec
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS= 0V)
Parameter
Symbol
Min
Typ.
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
VDD
VDDQ
VIH
VIL
VTT
VREF
2.3
2.3
VREF + 0.15
-0.3
VREF - 0.04
0.49*VDDQ
2.5
2.5
-
-
VREF
0.5*VDDQ
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
Max
2.7
2.7
VDDQ + 0.3
VREF - 0.15
VREF + 0.04
0.51*VDDQ
Unit
V
V
V
V
V
V
Note
1
2
3
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
0.7
0.5*VDDQ-0.2
VREF - 0.31
VDDQ + 0.6
0.5*VDDQ+0.2
V
V
V
V
1
2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2 / Feb. 2004
5
5 Page 
www.DataSheet4U.com
HYMD512G726A(L)4-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
Parameter
-M(DDR2662-2-2) -K(DDR266A)
Symbol
Min Max Min Max
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0 -
Input Pulse Width
tIPW
2.2
-
2.2 -
Write DQS High Level Width
tDQSH 0.35 - 0.35 -
Write DQS Low Level Width
tDQSL 0.35 - 0.35 -
Clock to First Rising edge of
DQS-In
tDQSS 0.75 1.28 0.75 1.25
Data-In Setup Time to DQS-In
(DQ & DM)
tDS 0.5
-
0.5 -
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.5
-
0.5 -
DQ & DM Input Pulse Width
tDIPW 1.75 - 1.75 -
Read DQS Preamble Time
tRPRE 0.9 1.1 0.9 1.1
Read DQS Postamble Time
tRPST 0.4 0.6 0.4 0.6
Write DQS Preamble Setup Time tWPRES 0 - 0 -
Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 -
Write DQS Postamble Time
tWPST 0.4 0.6 0.4 0.6
Mode Register Set Delay
tMRD
2
-
2-
Exit Self Refresh to Any Execute
Command
tXSC
200
-
200 -
Average Periodic Refresh Interval tREFI
-
7.8
- 7.8
-H(DDR266B)
Min Max
1.0 -
2.2 -
0.35 -
0.35 -
0.75 1.25
0.5 -
0.5 -
1.75
0.9
0.4
0
0.25
0.4
2
-
1.1
0.6
-
-
0.6
-
200 -
- 7.8
-L(DDR200)
Min Max
1.1 -
2.5 -
0.35 -
0.35 -
Unit Note
ns
2,4,5,
6
ns 6
CK
CK
0.75 1.25 CK
0.6
-
ns
6,7,
11~13
0.6
-
ns
6,7,
11~13
2 - ns
0.9 1.1 CK
0.4 0.6 CK
0 - CK
0.25 - CK
0.4 0.6 CK
2 - CK
200 - CK 8
- 7.8 us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps ps
0.5 0 0
0.4 +50 0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
Rev. 0.2 / Feb. 2004
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HYMD512G726AM4-H.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HYMD512G726AM4-H | Registered DDR SDRAM DIMM | Hynix Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |