PDF HYMD116M725BH8-H Data sheet ( Hoja de datos )

Número de pieza	HYMD116M725BH8-H
Descripción	Unbuffered DDR SDRAM SO-DIMM
Fabricantes	Hynix Semiconductor
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No Preview Available ! DESCRIPTION www.DataSheet4U.com 16Mx72 bits Unbuffered DDR SDRAM SO-DIMM HYMD116M725B(L)8-J/M/K/H/L PRELIMINARY Hynix HYMD116M725B(L)8-J/M/K/H/L series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline Dual In-Line Memory Modules (SO-DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD116M725B(L)8-J/M/K/H/L series consists of nine 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 200pin glass-epoxy substrate. Hynix HYMD116M725B(L)8-J/M/K/H/L series provide a high performance 8-byte interface in 67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD116M725B(L)8-J/M/K/H/L series is designed for high speed of up to 166MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. Hynix HYMD116M725B(L)8-J/M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden- tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer. FEATURES • 128MB (16M x 72) Unbuffered DDR SO-DIMM based on 16Mx8 DDR SDRAM • JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) • 2.5V +/- 0.2V VDD and VDDQ Power supply • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz/166MHz • All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock • Data(DQ), Data strobes and Write masks latched on both rising and falling edges of the clock ORDERING INFORMATION • Data inputs on DQS centers when write (centered DQ) • Data strobes synchronized with output data for read and input data for write • Programmable CAS Latency 2 / 2.5 supported • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • tRAS Lock-out function supported • Internal four bank operations with single pulsed RAS • Auto refresh and self refresh supported • 4096 refresh cycles / 64ms Part No. Power Supply Clock Frequency Interface Form Factor HYMD116M725B(L)8-J HYMD116M725B(L)8-M HYMD116M725B(L)8-K HYMD116M725B(L)8-H HYMD116M725B(L)8-L VDD=2.5V VDDQ=2.5V 166MHz (DDR333) 133MHz (DDR266:2-2-2) 133MHz (DDR266A) 133MHz (DDR266B) 125MHz (DDR200) SSTL_2 200pin Unbuffered SO-DIMM JEDEC Defined Specifications compliant This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2/Aug. 02 1 1 page www.DataSh HYMD116M725B(L)8-J/M/K/H/L AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VS=0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns Ω Ω pF Rev. 0.2/Aug. 02 5 5 Page www.DataSheet4U.com HYMD116M725B(L)8-J/M/K/H/L AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) <DDR266A/B, DDR200> Parameter Symbol DDR266A Min Max DDR266B Min Max DDR200 Min Max Unit Note Row Cycle Time tRC 65 - 65 - 70 - ns Auto Refresh Row Cycle Time tRFC 75 - 75 - 80 - ns Row Active Time tRAS 45 120K 45 120K 50 120k ns Active to Read with Auto Precharge Delay tRAP 20 - 20 - 20 - ns 16 Row Address to Column Address Delay tRCD 20 - 20 - 20 - ns Row Active to Row Active Delay tRRD 15 - 15 - 15 - ns Column Address to Column Address Delay tCCD 1 - 1 - 1 - CK Row Precharge Time tRP 20 - 20 - 20 - ns Write Recovery Time tWR 15 - 15 - 15 - ns Write to Read Command Delay tWTR 1 - 1 - 1 - CK Auto Precharge Write Recovery + Precharge Time (tWR/tCK) (tWR/tCK) (tWR/tCK) tDAL + - +-+- (tRP/tCK) (tRP/tCK) (tRP/tCK) CK 15 System Clock Cycle Time CL = 2.5 CL = 2 7.5 12 7.5 12 8.0 12 ns tCK 7.5 12 10 12 10 12 ns Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CK Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CK Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.8 0.8 ns DQS-Out edge to Data-Out edge Skew tDQSQ - 0.5 - 0.5 - 0.6 ns Data-Out hold time from DQS tQH tHP -tQHS - tHP -tQHS - tHP -tQHS - ns 1, 10 Clock Half Period tHP min (tCL,tCH) - min (tCL,tCH) - min (tCL,tCH) - ns 1,9 Data Hold Skew Factor tQHS - 0.75 - 0.75 - 0.75 ns 10 Valid Data Output Window tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns Data-out high-impedance window from CK, /CK tHZ -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17 Data-out low-impedance window from CK, /CK tLZ -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17 Input Setup Time (fast slew rate) tIS 0.9 - 0.9 - 1.1 - ns 2,3,5,6 Input Hold Time (fast slew rate) tIH 0.9 - 0.9 - 1.1 - ns 2,3,5,6 Input Setup Time (slow slew rate) tIS 1.0 - 1.0 - 1.1 - ns 2,4,5,6 Input Hold Time (slow slew rate) tIH 1.0 - 1.0 - 1.1 - ns 2,4,5,6 Input Pulse Width tIPW 2.2 2.2 2.5 - ns 6 Write DQS High Level Width tDQSH 0.35 - 0.35 - 0.35 - CK Rev. 0.2/Aug. 02 11 11 Page

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