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PDF HMT125V7AFP8C Data sheet ( Hoja de datos )
| Número de pieza | HMT125V7AFP8C | |
| Descripción | 240pin DDR3 SDRAM VLP Registered DIMM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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240pin DDR3 SDRAM VLP Registered DIMM
DDR3 SDRAM VLP
Registered DIMM
Based on 1Gb A version
HMT112V7AFP8C
HMT125V7AFP8C
HMT125V7AFP4C
HMT351V7AMP4C
** Contents may be changed at any time without any notice.
Rev. 0.2 / December 2008
1
1 page  
www.DataShe
1.2 Speed Grade & Key Parameters
MT/S
Grade
tCK (min)
CAS Latency
tRCD (min)
tRP (min)
tRAS (min)
tRC (min)
CL-tRCD-tRP
DDR3-1066
-G7
1.875
7
13.125
13.125
37.5
50.625
7-7-7
DDR3-1333
-H9
1.5
9
13.5
13.5
36
49.5
9-9-9
1.3 Address Table
Organization
Refresh Method
Row Address
Column Address
Bank Address
Page Size
# of Rank
# of Device
1GB(1Rx8)
128M x 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
1
9
2GB(2Rx8)
256M x 72
8K/64ms
A0-A13
A0-A9
BA0-BA2
1KB
2
18
2GB(1Rx4)
256M x 72
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
1
18
Unit
ns
tCK
ns
ns
ns
ns
tCK
4GB(2Rx4)
512M x 72
8K/64ms
A0-A13
A0-A9,A11
BA0-BA2
1KB
2
36
Rev. 0.2 / December 2008
5
5 Page 
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3. Functional Block Diagram
3.1 1GB, 128Mx72 Module(1Rank of x8)
DQS8_t
DQS8_c
DM8/DQS17_t
DQS17_c
CB[7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D8
ZQ
DQS4_t
DQS_t
DQS4_c
DQS_c
DM4/DQS13_t
DQS13_c
TDQS_t
TDQS_c
D4
DQ[39:32]
DQ [7:0]
ZQ
DQS3_t
DQS3_c
DM3/DQS12_t
DQS12_c
DQ[31:24]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D3
ZQ
DQS5_t
DQS_t
DQS5_c
DQS_c
DM5/DQS14_t
DQS14_c
TDQS_t
TDQS_c
D5
DQ[47:40]
DQ [7:0]
ZQ
DQS2_t
DQS2_c
DM2/DQS11_t
DQS11_c
DQ[23:16]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D2
ZQ
DQS6_t
DQS_t
DQS6_c
DQS_c
DM6/DQS15-t
DQS15_c
TDQS_t
TDQS_c
D6
DQ[55:48]
DQ [7:0]
ZQ
DQS1_t
DQS1_c
DM1/DQS10_t
DQS10_c
DQ[15:8]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D1
DQS _t
DQS _c
DM /DQS9_t
DQS9_c
DQ[7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D0
Vtt
ZQ
DQS7_t
DQS_t
DQS7_c
DQS_c
DM7/DQS16_t
DQS16_c
TDQS_t
TDQS_c
D7
DQ[63:56]
DQ [7:0]
ZQ Vtt
ZQ
VDDSPD
VDD
VTT
VREFCA
VREFDQ
VSS
SPD
D0–D8
D0–D8
D0–D8
D0–D8
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are
1%.For all other resistor values refer to the
appropriate wiring diagram.
S0_n
S1_n
BA[N:0]
A[N:0]
RAS_n
CAS_n
WE_n
CKE0
ODT0
CK0_t
CK0_c
CK1_t
CK1_c
120
1%
120
1%
1:
2
R
E
G
I
S
T
E
R
/
P
L
L
RS0A_n CS0_n: SDRAMs D[3:0], D8
RS0BCK_n CS0_n: SDRAMs D[7:4]
RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D8
RBA[N:0]B BA[N:0]: SDRAMs D[7:4]
RA[N:0]A A[N:0]: SDRAMs D[3:0], D8
RA[N:0]B A[N:0]: SDRAMs D[7:4]
RRASA_n RAS_n: SDRAMs D[3:0], D8
RRASB_n RAS_n: SDRAMs D[7:4]
RCASA_n CAS_n: SDRAMs D[3:0], D8
RCASB_n CAS_n: SDRAMs D[7:4]
RWEA_n WE_n: SDRAMs D[3:0], D8
RWEB_n WE_n: SDRAMs D[7:4]
RCKE0A CKE0: SDRAMs D[3:0], D8
RCKE0B CKE0: SDRAMs D[7:4]
RODT0A ODT0: SDRAMs D[3:0], D8
RODT0B ODT0: SDRAMs D[7:4]
PCK0A_t CK_t: SDRAMs D[3:0], D8
PCK0B_t CK_t: SDRAMs D[7:4]
PCK0A_c CK_c: SDRAMs D[3:0], D8
PCK0B_c CK_c: SDRAMs D[7:4]
PAR_IN
OERR_n
RESET_n RST_n
Err_Out_n
RST_n: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330
VDDSPD
EVENT
SCL
SDA
VDDSPD
SA0
EVENT SPD with SA1
SCL Integrated SA2
SDA TS VSS
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
resistor to ground
Rev. 0.2 / December 2008
11
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