PDF HMT125U7TFR8C Data sheet ( Hoja de datos )

Número de pieza	HMT125U7TFR8C
Descripción	240pin DDR3 SDRAM Registered DIMM
Fabricantes	Hynix Semiconductor
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No Preview Available ! 240pin DDR3 SDRAM Regiwswtewr.DeadtaShDeIeMt4UM.com DDR3 SDRAM Unbuffered DIMMs Based on 1Gb T-Die HMT112U6TFR8C HMT112U7TFR8C HMT125U6TFR8C HMT125U7TFR8C * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 1.0 / Nov. 2009 1 1 page www.DataSheet4U.com Pin Descriptions Pin Name Description Pin Name Description A0–A15 BA0–BA2 RAS CAS WE S0–S1 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 DM0–DM8 CK0–CK1 CK0–CK1 SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) SCL SDA SA0–SA2 VDD* VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RSVD - I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use - *The VDD and VDDQ pins are tied common to a single power-plane on these designs Rev. 1.0 / Nov. 2009 5 5 Page www.DataSheet4U.com Functional Block Diagram 1GB, 128Mx64 Module(1Rank of x8) DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 BA0–BA2 A0–A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET S0 DQS4 DDMQS44 DM CS DQS DQS DQ0 I/O 0 DQ1 I/O 1 D0 DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 ZQ DQ7 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D1 ZQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D2 ZQ DQS5 DQS5 DM5 DQS6 DQS6 DM6 DQS7 DQS7 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D3 ZQ SCL BA0–BA2: SDRAMs D0–D7 A0–A15: SDRAMs D0–D7 RAS: SDRAMs D0–D7 CAS: SDRAMs D0–D7 CKE: SDRAMs D0–D7 WE: SDRAMs D0–D7 VDDSPD VDD/VDDQ ODT: SDRAMs D0–D7 VREFDQ CK: SDRAMs D0–D7 CK: SDRAMs D0–D7 RESET: SDRAMs D0-D7 VSS VREFCA Serial PD WP A0 A1 A2 SA0 SA1 SA2 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 ZQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D5 ZQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D6 ZQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D7 ZQ Notes: SDA 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relation- ships must be maintained as shown. 3. DQ,DM,DQS/DQS resistors;Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details SPD section of this document. D0–D7 5. Refer to Section 3.1 of this document for details on address mirroring. D0–D7 D0–D7 6. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% D0–D7 7. One SPD exists per module. Rev. 1.0 / Nov. 2009 11 11 Page

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