PDF HMT125R7AFP4C Data sheet ( Hoja de datos )

Número de pieza	HMT125R7AFP4C
Descripción	DDR3 SDRAM Registered DIMM Based on 1Gb A version
Fabricantes	Hynix Semiconductor
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No Preview Available ! www.DataSheet4U.com 240pin DDR3 SDRAM Registered DIMM DDR3 SDRAM Registered DIMM Based on 1Gb A version HMT112R7AFP8C HMT125R7AFP8C HMT125R7AFP4C HMT151R7AFP4C HMT151R7AFP8C HMT31GR7AMP4C ** Contents may be changed at any time without any notice. Rev. 0.4 /Jul. 2009 1 1 page www.DataSheet4 1.2 Key Parameters MT/s Grade tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 -H9 1.5 9 13.5 13.5 36 49.5 9-9-9 Unit ns tCK ns ns ns ns tCK 1.3 Speed Grade Grade -G7 -H9 CL5 CL6 800 800 Frequency [MHz] CL7 1066 1066 CL8 1066 1066 CL9 1333 CL10 1333 Remark 1.4 Address Table 1GB(1Rx8) 2GB(2Rx8) 2GB(1Rx4) 4GB(2Rx4) 4GB(4Rx8) 8GB(4Rx4) Organization Refresh Method Row Address Column Address Bank Address Page Size # of Rank # of Device 128M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 1 9 256M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 2 18 256M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 1 18 512M x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 2 36 512M x 72 8K/64ms A0-A13 A0-A9 BA0-BA2 1KB 4 36 1G x 72 8K/64ms A0-A13 A0-A9,A11 BA0-BA2 1KB 4 72 Rev. 0.4 / Jul. 2009 5 5 Page www.DataSheet4U.com 3. Functional Block Diagram 3.1 1GB, 128Mx72 Module(1Rank of x8) DQS8 DQS8 DM8/DQS17 DQS17 CB[7:0] DQS DQS TDQS TDQS DQ [7:0] D8 ZQ DQS4 DQS DQS4 DQS DM4/DQS13 DQS13 TDQS TDQS D4 DQ[39:32] DQ [7:0] ZQ DQS3 DQS3 DM3/DQS12 DQS12 DQ[31:24] DQS DQS TDQS TDQS DQ [7:0] D3 ZQ DQS5 DQS DQS5 DQS DM5/DQS14 DQS14 TDQS TDQS D5 DQ[47:40] DQ [7:0] ZQ DQS2 DQS2 DM2/DQS11 DQS11 DQ[23:16] DQS DQS TDQS TDQS DQ [7:0] D2 ZQ DQS6 DQS DQS6 DQS DM6/DQS15 DQS15 TDQS TDQS D6 DQ[55:48] DQ [7:0] ZQ DQS1 DQS1 DM1/DQS10 DQS10 DQ[15:8] DQS DQS TDQS TDQS DQ [7:0] D1 DQS DQS DM /DQS9 DQS9 DQ[7:0] DQS DQS TDQS TDQS DQ [7:0] D0 Vtt ZQ DQS7 DQS DQS7 DQS DM7/DQS16 DQS16 TDQS TDQS D7 DQ[63:56] DQ [7:0] ZQ Vtt ZQ VDDSPD VDD VTT VREFCA VREFDQ VSS SPD D0–D8 D0–D8 D0–D8 D0–D8 Note: 1.DQ-to-I/O wiring may be changed within byte. 2.ZQ resistors are 1%.For all other resistor values refer to the appropriate wiring diagram. S0 S1 BA[N:0] A[N:0] RAS CAS WE CKE0 ODT0 CK0 CK0 CK0 CK0 120 1% 120 1% 1: 2 R E G I S T E R / P L L RS0A CS0: SDRAMs D[3:0], D8 RS0B CS0: SDRAMs D[7:4] RBA[N:0]A BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]A BA[N:0]: SDRAMs D[7:4] RRAA[[NN::00]]AA A[N:0]: SDRAMs D[3:0], D8 A[N:0]: SDRAMs D[7:4] RRASA RAS: SDRAMs D[3:0], D8 RRASA RAS: SDRAMs D[7:4] RCASA CAS: SDRAMs D[3:0], D8 RCASA CAS: SDRAMs D[7:4] RWEA WE: SDRAMs D[3:0], D8 RWEA WE: SDRAMs D[7:4] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PAR_IN RESET OERR RST Err_Out RST: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330 VDDSPD EVENT SCL SDA VDDSPD SA0 EVENT SPD with SA1 SCL Integrated SA2 SDA TS VSS SA0 SA1 SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative resistor to ground Rev. 0.4 / Jul. 2009 11 11 Page

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