PDF ADUC7122 Data sheet ( Hoja de datos )

Número de pieza	ADUC7122
Descripción	Precision Analog Microcontroller
Fabricantes	Analog Devices
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Data Sheet Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU ADuC7122 FEATURES Analog I/O 13-external channel, 12-bit, 1 MSPS ADC 2 differential channels with programmable gain PGA (1 to 5) input range IOVDD power monitor channel On-chip temperature monitor 11 general-purpose inputs Fully differential and single-ended modes 0 V to VREF analog input range 12 × 12-bit voltage output DACs On-chip voltage reference: 1.2 V/2.5 V Buffered output reference sources for use with external circuits Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 41.78 MHz 41.78 MHz PLL with programmable divider Memory 126 kB Flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug Software-triggered in-circuit reprogrammability On-chip peripherals UART, 2× I2C and SPI serial I/Os 32-pin GPIO port 4 general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 40 mA at 41.78 MHz Packages and temperature range 7 mm × 7 mm 108-ball BGA Fully specified for −10°C to +95°C operation Tools Low cost QuickStart development system Full third-party support APPLICATIONS Optical networking, industrial control, and automation systems Smart sensors and precision instrumentation FUNCTIONAL BLOCK DIAGRAM AVDD 3.3V AGND DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 PADC0 PGA PADC1 PGA ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 TEMPERATURE IOVDD MON SENSOR INTERNAL REFERENCE BUF VREF_1.2 VREF_2.5 DAC BUF DAC9 DAC BUF DAC10 1MSPS 12-BIT SAR ADC ADuC7122 DAC BUF PLA OSC PLL POR PWM WAKE-UP TIMER WD TIMER VIC 3× GP TIMERS 126k FLASH (63k × 16-BIT) 8k SRAM (2k × 32-BIT) ARM7 TDMI LDO UART JTAG GPIO CONTROL SPI 12C × 2 P0.0 TO P0.7 P1.0 TO P1.7 Figure 1. P2.0 TO P2.7 P3.0 TO P3.7 DAC11 IOVDD IOGND XTALI XTALO RST TDO TDI TCK TMS TRST Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ADuC7122 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −10°C to +95°C, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy1, 2 Resolution Integral Nonlinearity Differential Nonlinearity3, 4 DC Code Distribution ENDPOINT ERRORS5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Single-Ended Mode Leakage Current Input Capacitance Input Capacitance PADC0 INPUT Full Scale Input Range Input Leakage at PADC0P4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC0P Compliant Range PADC1 INPUT Full Scale Input Range Input Leakage at PADC1P4 Resolution Gain Error4 Gain Drift4 Offset4 Offset Drift4 PADC1P Compliant Range Min Typ 5 12 ±0.6 ±0.5 1 ±2 ±1 ±2 ±1 69 −78 −75 −80 0.15 ±0.2 20 20 20 0.15 11 3 30 0.1 10.6 0.15 11 3 30 0.1 Max Unit μs Bits ±2 LSB +1.4/−0.99 LSB LSB ±5 LSB LSB ±5 LSB LSB dB dB dB dB Test Conditions/Comments Eight acquisition clocks and fADC/2 2.5 V internal reference, not production tested for PADC0/PADC1 channels 2.5 V internal reference, gauranteed monotonic ADC input is a dc voltage Internally unbuffered channels fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS internally unbuffered channels Includes distortion and noise components Measured on adjacent channels VCM6 ± VREF/2 0 to VREF AVDD − 1.5 V V V µA pF pF 1000 2 1 50 6 60 AVDD − 1.2 µA nA Bits % ppm/°C nA pA/°C V 700 2 1 50 6 60 AVDD − 1.2 µA nA Bits % ppm/°C nA pA/°C V See Table 35 and Table 36 Buffer bypassed Buffer enabled During ADC acquisition buffer bypassed During ADC acquisition buffer enabled 28.3 kΩ resistor, PGA gain = 3; acquisition time = 6 µs, pseudo differential mode 0.1% accuracy, 5 ppm external resistor for I to V PGA offset not included 53.5 kΩ resistor, PGA gain = 3; acquisition time = 6 µs, pseudo differential mode 0.1% accuracy, 5 ppm external resistor for I to V PGA offset not included Rev. A \| Page 5 of 96 5 Page Data Sheet ADuC7122 Table 5. SPI Master Mode Timing (SPICPH = 0) Parameter Description tSL SCLOCK low pulse width tSH SCLOCK high pulse width tDAV Data output valid after SCLOCK edge tDOSU Data output setup before SCLOCK edge tDSU Data input setup time before SCLOCK edge1 tDHD Data input hold time after SCLOCK edge tDF Data output fall time tDR Data output rise time tSR SCLOCK rise time tSF SCLOCK fall time Min 1 × tUCLK 2 × tUCLK 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) MOSI tSH tSL tDOSU tDAV tDF MSB tDR BITS 6 TO 1 Typ (SPIDIV + 1) × tUCLK (SPIDIV + 1) × tUCLK Max 25 75 5 12.5 5 12.5 5 12.5 5 12.5 tSR tSF LSB Unit ns ns ns ns ns ns ns ns ns ns MISO MSB IN BITS 6 TO 1 LSB IN tDSU tDHD Figure 4. SPI Master Mode Timing (SPICPH = 0) Rev. A \| Page 11 of 96 11 Page

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