PDF LC72323 Data sheet ( Hoja de datos )

Número de pieza	LC72323
Descripción	Single-Chip Microcontroller with PLL and LCD Driver
Fabricantes	Sanyo Semicon Device
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No Preview Available ! Ordering number : EN4950A CMOS LSI LC72323 Single-Chip Microcontroller with PLL and LCD Driver Overview The LC72323 is a single-chip microcontroller for use in electronic tuning applications. It includes on chip both LCD drivers and a PLL circuit that can operate at up to 150 MHz. It features a highly efficient instruction set, and powerful hardware. Functions • Stack: Eight levels • Fast programmable divider • General-purpose counters: HCTR for frequency measurement and LCTR for frequency or period measurement • LCD driver for displays with up to 56 segments (1/2 duty, 1/2 bias) • Program memory (ROM): 3 k words by 16 bits • Data memory (RAM): 256 4-bit digits • All instructions are single-word instructions • Cycle time: 2.67 µs, 13.33 µs, or 40.00 µs (option) • Unlock FF: 0.55 µs detection, 1.1 µs detection • Timer FF: 1 ms, 5ms, 25ms, 125ms • Input ports: One dedicated key input port and one high-breakdown voltage port • Output ports: Two dedicated key output ports, one high-breakdown voltage open-drain port Two CMOS output ports (of which one can be switched to be used as LCD driver outputs) Seven CMOS output ports (mask option switchable to use as LCD ports) • I/O ports: One switchable between input and output in four-bit units and one switchable between input and output in one-bit units Note: Each port consists of four bits. • Program runaway can be detected and a special address set (Programmable watchdog timer). • Voltage detection type reset circuit • One 6-bit A/D converter • One external interrupt • Hold mode for RAM backup • Sense FF for hot/cold startup determination • PLL: 4.5 to 5.5 V • CPU: 3.5 to 5.5 V • RAM: 1.3 to 5.5 V • Package: QIP80E Package Dimensions unit: mm 3174-QFP80E [LC72323] SANYO: QFP80E This LSI can easily use CCB that is SANYO’s original bus format. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 32896HA (OT)/31595TH (OT) No. 4950-1/13 1 page LC72323 Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Rejected pulse width Power-down detection voltage Input high level current Input low level current Input floating voltage Pull-down resistance Output high level off leakage current Output low level off leakage current Output high level voltage Output low level voltage Output middle level voltage A/D conversion error Current drain Symbol Conditions VH PREJ VDET IIH1 IIH2 IIH3 IIH4 IIH5 IIL1 IIL2 IIL3 IIL4 VIF RPD IOFFH1 IOFFH2 IOFFH3 IOFFL1 IOFFL2 VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 VOL7 VOL8 VM1 IDD1 IDD2 IDD3 IDD4 IDD5 LCTR (period), RES, INT, PE1, PE3 SNS INT, HOLD, RES, ADI, SNS, and G port: VI = 5.5 V A, E, and F ports: E and F ports with outputs off, A port with no RPD, VI = VDD XIN: VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V A port: With an RPD, VI = VDD = 5.0 V INT, HOLD, RES, ADI, SNS, and the G port: VI = VSS A, E, and F ports: E and F ports with outputs off, A port with no RPD, VI = VSS XIN: VIN = VSS FMIN, AMIN, HCTR, LCTR: VI = VSS A port: With an RPD A port: With an RPD, VDD = 5.0 V EO1, EO2: VO = VDD B, C, D, E, F, and I ports: VO = VDD H port: VO = 13 V EO1, EO2: VO = VSS B, C, D, E, F, and I ports: VO = VSS B and C ports: IO = 1 mA E and F ports: IO = 1 mA EO1, EO2: IO = 500 µA XOUT: IO = 200 µA S1 to S28 and the I port: IO = –0.1 mA D port: IO = 5 mA COM1, COM2: IO = 25 µA B and C ports: IO = 50 µA E and F ports: IO = 1 mA EO1, EO2: IO = 500 µA XOUT: IO = 200 µA S1 to S28 and the I port: IO = 0.1 mA D port: IO = 5 mA COM1, COM2: IO = 25 µA H port: IO = 5 mA, VDD1 COM1, COM2: VDD = 5.0 V, IO = 25 µA ADI: VDD1 VDD1, fIN2 = 130 MHz VDD2, PLL stopped, CT = 2.67 µs (HOLD mode, Figure 1) VDD2, PLL stopped, CT = 13.33 µs (HOLD mode, Figure 1) VDD2, PLL stopped, CT = 40.00 µs (HOLD mode, Figure 1) VDD = 5.5 V, oscillator stopped, Ta = 25°C (BACK UP mode, Figure 2) VDD = 2.5 V, oscillator stopped, Ta = 25°C (BACK UP mode, Figure 2) min 0.1 VDD Ratings typ 2.7 3.0 max 50 3.3 Unit V µs V 3.0 µA 3.0 µA 2.0 5.0 15 µA 4.0 10 30 µA 50 µA 3.0 µA 3.0 µA 2.0 4.0 75 VDD – 2.0 VDD – 1.0 VDD – 1.0 VDD – 1.0 VDD – 1.0 VDD – 1.0 VDD – 0.75 0.5 0.3 (150 Ω) 0.75 2.0 –1/2 5.0 10 100 0.01 0.01 VDD – 1.0 15 30 0.05 VDD 200 10 3.0 5.0 10 3.0 VDD – 0.5 VDD – 0.5 VDD – 0.3 1.0 2.0 1.0 1.0 1.0 1.0 1.0 0.5 0.75 (400 Ω) 2.0 2.5 3.0 +1/2 15 20 µA µA V kΩ nA µA µA nA µA V V V V V V V V V V V V V V V V LSB mA 1.5 mA 1.0 mA 0.7 mA 5 µA 1 µA No. 4950-5/13 5 Page LC72323 LC72323 Instruction Table Abbreviations: ADDR: Program memory address [12 bits] b: Borrow B: Bank number [2 bits] C: Carry DH: Data memory address high (row address) [2 bits] DL: Data memory address low (column address) [4 bits] I: Immediate data [4 bits] M: Data memory address N: Bit position [4 bits] Pn: Port number [4 bits] r: General register (one of the locations 00 to 0FH in bank 0) Rn: Register number [4 bits] ( ): Contents of register or memory ( )N: Contents of bit N of register or memory Operand Mnemonic 1st 2nd Function AD ADS AC ACS AI AIS AIC AICS SU SUS SB SBS SI SIS SIB SIBS r M Add M to r Add M to r, r M then skip if carry r M Add M to r with carry Add M to r with carry, r M then skip if carry M I Add I to M Add I to M, M I then skip if carry M I Add I to M with carry Add I to M with carry, M I then skip if carry r M Subtract M from r Subtract M from r, r M then skip if borrow Subtract M from r with r M borrow Subtract M from r with r M borrow, then skip if borrow M I Subtract I from M Subtract I from M, M I then skip if borrow Subtract I from M with M I borrow Subtract I from M with M I borrow, then skip if borrow SEQ r M Skip if r equals M SGE r M Skip if r is greater than or equal to M SEQI M I Skip if M equal to I SGEI M I Skip if M is greater than or equal to I Operation r ← (r) + (M) r ← (r) + (M) skip if carry r ← (r) + (M) + C r ← (r) + (M) + C skip if carry M ← (M) + I M ← (M) + I skip if carry M ← (M) + I + C M ← (M) + I + C skip if carry r ← (r) – (M) r ← (r) – (M) skip if borrow r ← (r) – (M) – b r ← (r) – (M) – b skip if borrow M ← (M) – I M ← (M) – I skip if borrow M ← (M) – I – b M ← (M) – I – b skip if borrow r–M skip if zero r–M skip if not borrow (r) ≥ (M) M–I skip if zero M–I skip if not borrow (M) ≥ I Machine code D15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 0 1 0 0 0 0 DH DL Rn 0 1 0 0 0 1 DH 0 1 0 0 1 0 DH DL DL Rn Rn 0 1 0 1 1 1 DH 0 1 0 1 0 0 DH DL DL Rn I 0 1 0 1 0 1 DH 0 1 0 1 1 0 DH DL DL I I 0 1 0 1 1 1 DH 0 1 1 0 0 0 DH DL DL I Rn 0 1 1 0 0 1 DH DL Rn 0 1 1 0 1 0 DH DL Rn 0 1 1 0 0 0 DH 0 1 1 1 0 0 DH 0 1 1 1 0 1 DH 0 1 1 1 1 0 DH DL DL DL DL Rn I I I 0 1 0 1 1 1 DH DL I 0 0 0 0 0 1 DH DL Rn 0 0 0 0 1 1 DH DL Rn 0 0 1 1 0 1 DH DL I 0 0 1 1 1 1 DH DL I Continued on next page. No. 4950-11/13 11 Page

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