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PDF K4B1G0446C Data sheet ( Hoja de datos )
| Número de pieza | K4B1G0446C | |
| Descripción | 1Gb C-die DDR3 SDRAM Specification | |
| Fabricantes | Samsung semiconductor | |
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K4B1G04(08/16)46C
1Gb DDR3 SDRAM
www.DataSheet4U.com
1Gb C-die DDR3 SDRAM Specification
Revision 1.0
June 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Page 1 of 63
Rev. 1.0 June 2007
1 page  
K4B1G04(08/16)46C
3.0 Package pinout/Mechanical Dimension & Addressing
1Gb DDR3 SDRAM
www.DataSheet4U.com
3.1 x4 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls)
1 2 3 4 5 6 7 8 9 10 11
A NC
NC
NC
B
C
D
NC
VSS
VDD
NC
E
VSS
VSSQ
DQ0
F
VDDQ
DQ2
DQS
G
VSSQ
NC
DQS
H
VREFDQ VDDQ
NC
J
NC
VSS
RAS
K
ODT
VDD
CAS
L NC CS WE
M
VSS
BA0
BA2
N
VDD
A3
A0
P
VSS
A5
A2
R
VDD
A7
A9
T
NC
VSS
RESET
A13
U
V
W NC
NC
NC
NC NC NC
NC
DM
DQ1
VDD
NC
CK
CK
A10/AP
A15
A12/BC
A1
A11
NC
VSS
VSSQ
DQ3
VSS
NC
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
NC
NC
D
E
F
G
H
J
K
L
M
N
P
R
T
NC NC NC
Note1: A1,A2,A4,A8,A10,A11,D1,D11,T1,T11,W1,W2,W4,W8,W10 and W11 balls indicate mechanical support balls with no internal connection
Ball Locations (x4)
Populated ball
Ball not populated
Top view
(See the balls through the Package)
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Page 5 of 63
Rev. 1.0 June 2007
5 Page 
K4B1G04(08/16)46C
4.0 Input/Output Functional Description
1Gb DDR3 SDRAM
www.DataSheet4U.com
[ Table 3 ] Input/Output function description
Symbol
Type
Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and
output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or
Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become
stable during the power on and initialization sequence, it must be maintained during all operations (including Self-
Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT
and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on
systems with multiple Ranks. CS is considered part of the command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When
enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode
Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro-
grammed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
(DMU), (DML)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci-
dent with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of
DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1.
BA0 - BA2
Input
Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines if the mode register or extended mode register is to be accessed during a
MRS cycle.
A0 - A12
Input
Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands
to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions,
see below)
The address inputs also provide the op-code during Mode Register Set commands.
A10 / AP
Input
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per-
formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or
all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per-
formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details
RESET
Input
Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH.
RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and
20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low.
DQ Input/Output Data Input/ Output: Bi-directional data bus.
DQS, (DQS) Input/Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data.
TDQS, (TDQS)
Output
Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When
disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.
NC No Connect: No internal electrical connection is present.
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
DQ Power Supply: 1.5V +/- 0.075V
DQ Ground
Power Supply: 1.5V +/- 0.075V
Ground
VREFDQ
VREFCA
ZQ
Supply
Supply
Supply
Reference voltage for DQ
Reference voltage for CA
Reference Pin for ZQ calibration
Note : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.
Page 11 of 63
Rev. 1.0 June 2007
11 Page | ||
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