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PDF AD9547 Data sheet ( Hoja de datos )
| Número de pieza | AD9547 | |
| Descripción | Dual/Quad Input Network Clock Generator/Synchronizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Dual/Quad Input Network Clock
Generator/Synchronizer
AD9547
FEATURES
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Automatic/manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable
as a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 kHz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as
a single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
20-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
64-lead LFCSP package
APPLICATIONS
Network synchronization
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9547 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9547 generates an output clock that is synchronized to one
of two differential or four single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9547
continuously generates a clean (low jitter), valid output clock,
even when all references fail, by means of digitally controlled
loop and holdover circuitry.
The AD9547 operates over an industrial temperature range of
−40°C to +85°C.
STABLE
SOURCE
FUNCTIONAL BLOCK DIAGRAM
ANALOG
FILTER
CLOCK
MULTIPLIER
AD9547
REFERENCE INPUTS
AND
MONITOR MUX
DIGITAL
PLL
DAC
SYNC
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
SERIAL CONTROL INTERFACE
(SPI or I2C)
EEPROM
STATUS AND
CONTROL PINS
Figure 1.
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9547
Data Sheet
SPECIFICATIONS
Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for
AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1.8 V, TA = 25°C, IDAC = 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
DVDD3
DVDD
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
AVDD
Min
3.135
1.71
3.135
3.135
1.71
1.71
Typ
3.30
1.80
3.30
3.30
1.80
1.80
Max Unit Test Conditions/Comments
3.465 V
Pin 7, Pin 58
1.89 V
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
3.465 V
Pin 16, Pin 33, Pin 43, Pin 49
3.465 V
Pin 25, Pin 31
1.89 V
Pin 25, Pin 31
1.89 V
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
SUPPLY CURRENT
The test conditions for the maximum supply current are the same as the test conditions for the All Blocks Running section of Table 3. The
test conditions for the typical supply current are the same as the test conditions for the Typical Configuration section of Table 3.
Table 2.
Parameter
IDVDD3
IDVDD
IAVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
IAVDD
Min Typ Max Unit Test Conditions/Comments
1.5 3
mA Pin 7, Pin 58
190 215 mA Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
52 70 mA Pin 16, Pin 33, Pin 43, Pin 49
24 55 mA Pin 25, Pin 31
24 55 mA Pin 25, Pin 31
135 150 mA Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
POWER DISSIPATION
Table 3.
Parameter
TYPICAL CONFIGURATION
Min Typ
800
ALL BLOCKS RUNNING
900
FULL POWER-DOWN
13
INCREMENTAL POWER DISSIPATION
SYSCLK PLL Off
Input Reference On
Differential
Single-Ended
Output Distribution Driver On
LVDS
LVPECL
CMOS
−105
7
13
70
75
65
1 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins.
2 fS is the sample rate of the output DAC.
3 fDDS is the output frequency of the DDS.
Max Unit Test Conditions/Comments
1100 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 122.88 MHz3; one LVPECL clock
distribution output running at 122.88 MHz (all others powered
down); one input reference running at 100 MHz (all others
powered down)
1250 mW fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock distribution
outputs configured as LVPECL at 399 MHz; all input references
configured as differential at 100 MHz; fractional-N active (R = 10,
S = 39, U = 9, V = 10)
mW Conditions = typical configuration; no external pull-up or
pull-down resistors
Conditions = typical configuration; table values show the change
in power due to the indicated operation
mW fSYSCLK = 1 GHz1; high frequency direct input mode
mW
mW
mW
mW
mW Single 3.3 V CMOS output with a 10 pF load
Rev. G | Page 4 of 106
5 Page 
AD9547
Data Sheet
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
EEPROM-TO-REGISTER DOWNLOAD TIME
Min
REGISTER-TO-EEPROM UPLOAD TIME
MINIMUM POWER-DOWN EXIT TIME
MAXIMUM TIME FROM ASSERTION OF THE RESET PIN
TO THE M0 TO M7 PINS ENTERING HIGH
IMPEDANCE STATE
Typ Max Unit
25 ms
200 ms
10.5 µs
45 ns
Test Conditions/Comments
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
Dependent on loop filter bandwidth
DIGITAL PLL
Table 14.
Parameter
PHASE FREQUENCY DETECTOR (PFD) INPUT
FREQUENCY RANGE
LOOP BANDWIDTH
PHASE MARGIN
REFERENCE INPUT (R) DIVISION FACTOR
INTEGER FEEDBACK (S) DIVISION FACTOR
FRACTIONAL FEEDBACK DIVIDE RATIO
Min
0.001
0.001
30
1
8
0
Typ
Max Unit
10 MHz
Test Conditions/Comments
Maximum fPFD = fS/1001, 2
1 × 105
89
230
220
0.999
Hz
Degrees
Programmable design parameter;
maximum fLOOP = fREF/(20R)3
Programmable design parameter
1, 2, …1,073,741,824
8, 9, …1,048,576
Maximum value = 1022/1023
1 fPFD is the frequency at the input to the phase-frequency detector.
2 fS is the sample rate of the output DAC.
3 fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
Min
0.001
0.001
Typ
1
1
Max Unit
65.5 ns
ps
16,700 ns
ps
Test Conditions/Comments
Reference-to-feedback period difference
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
FREQUENCY ACCURACY
Min Typ Max Unit
<0.01
ppb
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference
prior to entering holdover
Rev. G | Page 10 of 106
11 Page | ||
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| PDF Descargar | [ Datasheet AD9547.PDF ] | |
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