PDF MAX3639 Data sheet ( Hoja de datos )

Número de pieza	MAX3639
Descripción	Programmable Clock Generator
Fabricantes	Maxim Integrated Products
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No Preview Available ! 19-4911; Rev 0; 10/09 EVAALVUAAILTAIOBNLEKIT www.DataSheet4U.com Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs General Description The MAX3639 is a highly flexible, precision phase- locked loop (PLL) clock generator optimized for the next generation of network equipment that demands low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power-supply noise rejection, and pin-programmable LVDS/LVPECL output interfaces. The MAX3639 provides nine differential outputs and one LVCMOS output, divided into three banks. The fre- quency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock dis- tribution ICs on a system board, saving cost and space. This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -40°C to +85°C. Ethernet Switch/Router Wireless Base Station SONET/SDH Line Cards Applications PCIeM, Network Processors Fibre Channel SAN Typical Application Circuits and Pin Configuration appear at end of data sheet. Features S Inputs Crystal Interface: 18MHz to 33.5MHz LVCMOS Input: 15MHz to 160MHz Differential Input: 15MHz to 350MHz S Outputs LVCMOS Output: Up to 160MHz LVPECL/LVDS Outputs: Up to 800MHz S Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable Output Interface S Wide VCO Tuning Range (3.60GHz to 4.025GHz) S Low Phase Jitter 0.34psRMS (12kHz to 20MHz) 0.14psRMS (1.875MHz to 20MHz) S Excellent Power-Supply Noise Rejection S -40NC to +85NC Operating Temperature Range S +3.3V Supply Ordering Information PART TEMP RANGE PIN-PACKAGE MAX3639ETM+ -40NC to +85NC 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Functional Diagram XOUT XIN CIN XO LVCMOS LVPECL DIN DIN MAX3639 PLL, DIVIDERS, MUXES VCO LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVCMOS QA0 QA0 QA1 QA1 QA2 QA2 QA3 QA3 QA4 QA4 QB0 QB0 QB1 QB1 QB2 QB2 QC QC QCC PCIe is a registered trademark of PCI-SIG Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page www.DataSheet4U.com Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS fOFFSET = 1kHz -123 SSB Phase Noise at 125MHz fOFFSET = 10kHz fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz -124 -130 -147 -153 dBc/ Hz SSB Phase Noise at 100MHz fOFFSET = 1kHz fOFFSET = 10kHz fOFFSET = 100kHz fOFFSET = 1MHz -126 -127 -133 -148 dBc/ Hz fOFFSET R 10MHz -152 Note 1: A series resistor of up to 10.5I is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V Q5%. See Figure 3. Note 2: Measured with all outputs enabled and unloaded. Note 3: CIN can be AC- or DC-coupled. See Figure 8. Input high voltage must be ≤ VCC + 0.3V. Note 4: DIN can be AC- or DC-coupled. See Figure 10. Note 5: Measured with 100I differential load. Note 6: Measured with crystal input, or with 50% duty cycle LVCMOS or differential input. Note 7: Measured with output termination of 50I to VCC - 2V or Thevenin equivalent. Note 8: Measured with a series resistor of 33I to a load capacitance of 3.0pF. See Figure 1. Note 9: Measured at 156.25MHz. Note 10: Measured using LVCMOS/LVTTL input with slew rate R 1.0V/ns, or differential input with slew rate R 0.5V/ns. Note 11: Measured at 156.25MHz output with 200kHz, 50mVP-P sinusoidal signal on the supply using the crystal input and the power-supply filter shown in Figure 3. See the Typical Operating Characteristics for other supply noise frequen- cies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers. Note 12: Measured with all outputs enabled and all three banks at different frequencies. LVCMOS QCC 33Ω Z = 50Ω MAX3639 Figure 1. LVCMOS Output Measurement Setup 499Ω 0.1µF 3pF Z = 50Ω OSCILLOSCOPE 50Ω 5 5 Page www.DataSheet4U.com Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs output interface. A PLL bypass mode is also available for system testing or clock distribution. (see the Applications Information section). No signal should be applied to DIN if not used. Crystal Oscillator The on-chip crystal oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between XIN and XOUT. See the Crystal Selection and Layout section for more information. The XIN and XOUT pins can be left open if not used. LVCMOS Clock Input An LVCMOS-compatible clock source can be connected to CIN to serve as the PLL reference clock. The input is internally biased to allow AC- or DC-coupling (see the Applications Information section). It is designed to oper- ate from 15MHz to 160MHz. No signal should be applied to CIN if not used. Differential Clock Input A differential clock source can be connected to DIN to serve as the PLL reference clock. This input oper- ates from 15MHz to 350MHz and contains an internal 100ω differential termination. This input can accept DC-coupled LVPECL signals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals Phase-Locked Loop (PLL) The PLL takes the signal from the crystal oscillator, LVCMOS clock input, or differential clock input and syn- thesizes a low-jitter, high-frequency clock. The PLL con- tains a phase-frequency detector (PFD), a charge pump (CP), and two low phase noise VCOs that combined give a wide 3.60GHz to 4.025GHz frequency range. The high-frequency VCO output is divided by prescale divider P and then is connected to the PFD input through a feedback divider F. The PFD compares the reference frequency to the divided-down VCO output and gener- ates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO/P output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies. Dividers and Muxes The dividers and muxes are set with three-level control inputs. Divider settings and routing information are given in Tables 1 to 7. See Table 11 for example divider con- figurations used in various applications. Table 1. PLL Input IN_SEL 0 1 NC INPUT Crystal Input. XO circuit is disabled when not selected. Differential Input. No signal should be applied to DIN if not selected LVCMOS Input. No signal should be applied to CIN if not selected. Table 2. PLL Bypass PLL_BP 0 1 NC PLL OPERATION PLL Enabled for Normal Operation. All outputs from the A, B, and C banks are derived from the VCO. PLL Bypassed. Selected input passes directly to the outputs. Both VCOs are disabled to minimize power con- sumption and intermodulation spurs. Used for system testing or clock distribution. The outputs from A-bank and B-bank are derived from the VCO, but the C-bank outputs are directly driven from the input signal for purposes of daisy chaining. 11 11 Page

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