MAX3638 Datasheet PDF - Maxim Integrated Products
| Part Number | MAX3638 | |
| Description | Programmable Clock Generator | |
| Manufacturers | Maxim Integrated Products | |
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19-4910; Rev 0; 10/09
EVAALVUAAILTAIOBNLEKIT
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Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
General Description
The MAX3638 is a highly flexible, precision phase-
locked loop (PLL) clock generator optimized for the next
generation of network equipment that demands low-jitter
clock generation and distribution for robust high-speed
data transmission. The device features subpicosecond
jitter generation, excellent power-supply noise rejection,
and pin-programmable LVDS/LVPECL output interfaces.
The MAX3638 provides nine differential outputs and
one LVCMOS output, divided into three banks. The fre-
quency and output interface of each output bank can be
individually programmed, making this device an ideal
replacement for multiple crystal oscillators and clock dis-
tribution ICs on a system board, saving cost and space.
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN
package and operates from -40°C to +85°C.
Ethernet Switch/Router
Wireless Base Station
Applications
PCIeM, Network
Processors
DDR/QDR Memory
Typical Application Circuits and Pin Configuration appear at
end of data sheet.
Features
S Inputs
Crystal Interface: 18MHz to 33.5MHz
LVCMOS Input: 15MHz to 160MHz
Differential Input: 15MHz to 350MHz
S Outputs
LVCMOS Output: Up to 160MHz
LVPECL/LVDS Outputs: Up to 800MHz
S Three Individual Output Banks
Pin-Programmable Dividers
Pin-Programmable Output Interface
S Wide VCO Tuning Range (3.83GHz to 4.025GHz)
S Low Phase Jitter
0.34psRMS (12kHz to 20MHz)
0.14psRMS (1.875MHz to 20MHz)
S Excellent Power-Supply Noise Rejection
S -40NC to +85NC Operating Temperature Range
S +3.3V Supply
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3638ETM+
-40NC to +85NC
48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Functional Diagram
XOUT
XIN
CIN
XO
LVCMOS
DIN
DIN
MAX3638
PLL, DIVIDERS, MUXES
VCO
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVPECL/LVDS
LVCMOS
QA0
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
QB2
QC
QC
QCC
PCIe is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SSB Phase Noise at 66.67MHz
fOFFSET = 1kHz
fOFFSET = 10kHz
fOFFSET = 100kHz
fOFFSET = 1MHz
fOFFSET R 10MHz
-130
-131
-137
-152
-156
dBc/
Hz
Note 1: A series resistor of up to 10.5I is allowed between VCC and VCCA for filtering supply noise when system power-supply
tolerance is VCC = 3.3V Q5%. See Figure 3.
Note 2: Measured with all outputs enabled and unloaded.
Note 3: CIN can be AC- or DC-coupled. See Figure 8. Input high voltage must be ≤ VCC + 0.3V.
Note 4: DIN can be AC- or DC-coupled. See Figure 10.
Note 5: Measured with 100I differential load.
Note 6: Measured with crystal input, or with 50% duty cycle LVCMOS or differential input.
Note 7: Measured with output termination of 50I to VCC - 2V or Thevenin equivalent.
Note 8: Measured with a series resistor of 33I to a load capacitance of 3.0pF. See Figure 1.
Note 9: Measured at 125MHz output.
Note 10: Measured using LVCMOS/LVTTL input with slew rate R 1.0V/ns, or differential input with slew rate R 0.5V/ns.
Note 11: Measured at 125MHz output with 200kHz, 50mVP-P sinusoidal signal on the supply using the crystal input and the
power-supply filter shown in Figure 3. See the Typical Operating Characteristics for other supply noise frequen-
cies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to
Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers.
Note 12: Measured with all outputs enabled and all three banks at different frequencies.
LVCMOS QCC
33Ω
Z = 50Ω
MAX3638
Figure 1. LVCMOS Output Measurement Setup
499Ω 0.1µF
3pF
Z = 50Ω
OSCILLOSCOPE
50Ω
5
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| Information | Total 22 Pages | |
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