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PDF MAX3624A Data sheet ( Hoja de datos )
| Número de pieza | MAX3624A | |
| Descripción | Precision Clock Generator | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-5005; Rev 0; 10/09
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Low-Jitter, Precision Clock Generator
with Four Outputs
General Description
The MAX3624A is a low-jitter, precision clock generator
optimized for networking applications. The device inte-
grates a crystal oscillator and a phase-locked loop
(PLL) clock multiplier to generate high-frequency clock
outputs for Ethernet, Fibre Channel, SONET/SDH, and
other networking applications.
Maxim’s proprietary PLL design features ultra-low jitter
(0.36psRMS) and excellent power-supply noise rejec-
tion, minimizing design risk for network equipment.
The MAX3624A has three LVPECL outputs and one
LVCMOS output. Selectable output dividers and a
selectable feedback divider allow a range of output
frequencies.
Applications
Ethernet Networking Equipment
Fibre Channel Storage Area Network
SONET/SDH Network
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
IN_SEL
MR
Features
♦ Crystal Oscillator Interface: 19.375MHz to 27MHz
♦ CMOS Input: 19MHz to 40.5MHz
♦ Output Frequencies
Ethernet: 62.5MHz, 125MHz, 156.25MHz,
312.5MHz
Fibre Channel: 106.25MHz, 159.375MHz,
212.5MHz, 318.5MHz
SONET/SDH: 77.76MHz, 155.52MHz, 311.04MHz
♦ Low Jitter
0.14psRMS (1.875MHz to 20MHz)
0.36psRMS (12kHz to 20MHz)
♦ Excellent Power-Supply Noise Rejection
♦ No External Loop Filter Capacitor Required
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3624AETJ+
-40°C to +85°C
32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Block Diagram
BYPASS
SELA[1:0]
REF_IN
27pF
X_IN
X_OUT
33pF
SELA[1:0]
SELB[1:0]
FB_SEL[1:0]
BYPASS
RESET LOGIC/POR
RESET
LVCMOS
0
CRYSTAL
OSCILLATOR
1
PFD
DIVIDERS:
M = 16, 24, 25, 32
NA = 1, 2, 3, 4, 5, 6, 8, 10, 12
NB = 1, 2, 3, 4, 5, 6, 8, 10, 12
0
620MHz TO 648MHz
FILTER
VCO
1
RESET
DIVIDER
M
MAX3624A
DIVIDER
NA
RESET
LVCMOS
BUFFER
LVPECL
BUFFER
RESET
DIVIDER
NB
LVPECL
BUFFER
LVPECL
BUFFER
QAC_OE
QA_C
QA_OE
QA
QA
QB1_OE
QB1
QB1
QB0_OE
QB0
QB0
FB_SEL[1:0]
SELB[1:0]
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Low-Jitter, Precision Clock Generator
with Four Outputs
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25°C, crystal frequency = 25MHz.)
SUPPLY CURRENT
vs. TEMPERATURE
250
225
200
175 ALL OUTPUTS ACTIVE AND TERMINATED
150
125
100 ALL OUTPUTS ACTIVE AND UNTERMINATED
75
50
25
0
-40
-15 10 35 60
AMBIENT TEMPERATURE (°C)
85
-80
-90
-100
-110
-120
-130
-140
-150
-160
0.1
PHASE NOISE AT 312.5MHz
CLOCK FREQUENCY
1 10 100 1000 10,000 100,000
OFFSET FREQUENCY (kHz)
DIFFERENTIAL OUTPUT WAVEFORM
AT 156.25MHz (LVPECL OUTPUT)
MAX3624A toc02
1ns/div
-80
-90
-100
-110
-120
-130
-140
-150
-160
0.1
PHASE NOISE AT 125MHz
CLOCK FREQUENCY
1 10 100 1000 10,000 100,000
OFFSET FREQUENCY (kHz)
OUTPUT WAVEFORM AT 125MHz
(LVCMOS OUTPUT)
MAX3624A toc03
MEASURED USING 50Ω OSCILLOSCOPE INPUT
THROUGH NETWORK SHOWN IN FIGURE 1
-80
-90
-100
-110
-120
-130
-140
-150
-160
0.1
1ns/div
PHASE NOISE AT 212.5MHz
CLOCK FREQUENCY
(26.5625MHz CRYSTAL)
1 10 100 1000 10,000 100,000
OFFSET FREQUENCY (kHz)
NOISE SPUR AMPLITUDE
vs. NOISE FREQUENCY
0
fC = 156.25MHz
-10 NOISE AMPLITUDE = 40mVP-P
-20
-30
-40
-50
-60
-70
-80
-90
10
100 1000
NOISE FREQUENCY (kHz)
10,000
_______________________________________________________________________________________ 5
5 Page 
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Low-Jitter, Precision Clock Generator
with Four Outputs
DISABLE
VDDO_A
10Ω
IN QA_C
10Ω
ESD
STRUCTURES
Figure 9. Simplified LVCMOS Output Circuit Schematic
Layout Considerations
The inputs and outputs are critical paths for the
MAX3624A, and care should be taken to minimize dis-
continuities on these transmission lines. Here are some
suggestions for maximizing the MAX3624A’s perfor-
mance:
• An uninterrupted ground plane should be posi-
tioned beneath the clock I/Os.
• Ground pin vias should be placed close to the IC
and the input/output interfaces to allow a return
current path to the MAX3624A and the receive
devices.
• Supply decoupling capacitors should be placed
close to the MAX3624A supply pins.
• Maintain 100Ω differential (or 50Ω single-ended)
transmission line impedance out of the MAX3624A.
• Use good high-frequency layout techniques and a
multilayer board with an uninterrupted ground
plane to minimize EMI and crosstalk.
Refer to the MAX3624A Evaluation Kit for more information.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN package pro-
vides a very low inductance path for return current trav-
eling to the PCB ground plane. The pad is also
electrical ground on the MAX3624A and must be sol-
dered to the circuit board ground for proper electrical
performance.
Pin Configuration
TOP VIEW
32 31 30 29 28 27 26 25
VCCO_B 1
GND 2
+
24 GND
23 QB1_OE
QB0_OE 3
22 SELA1
SELB1 4
SELB0 5
MAX3624A
21 SELA0
20 QA_OE
QAC_OE 6
MR 7
*EP
19 GND
18 VCC
GNDO_A 8
17 VCCA
9 10 11 12 13 14 15 16
THIN QFN
(5mm × 5mm)
*EXPOSED PAD CONNECTED TO GROUND.
Chip Information
TRANSISTOR COUNT: 10,780
PROCESS: BiCMOS
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MAX3624A.PDF ] | |
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