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PDF PCKEP14 Data sheet ( Hoja de datos )
| Número de pieza | PCKEP14 | |
| Descripción | 2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver | |
| Fabricantes | NXP Semiconductors | |
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PCKEP14
www.DataSheet4U.com
2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver
Rev. 01 — 30 October 2002
Product data
1. Description
The PCKEP14 is a low skew 1-to-5 differential driver, designed with clock distribution
in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input
signals can be either differential or single-ended (if the VBB output is used). HSTL
inputs can be used when the PCKEP14 is operating under PECL conditions.
The PCKEP14 specifically guarantees low output-to-output skew. Optimal design,
layout, and processing minimize skew within a device, and from device to device.
To ensure that the tight skew specification is realized, both sides of any differential
output need to be terminated identically into 50 Ω resistors, even if only one output is
being used. If an output pair is unused, both outputs may be left open (unterminated)
without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW
state. This avoids a runt clock pulse when the device is enabled/disabled, as can
happen with an asynchronous control. The internal flip-flop is clocked on the falling
edge of the input clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
The PCKEP14, as with most other ECL devices, can be operated from a positive VCC
supply in PECL mode. This allows the PCKEP14 to be used for high performance
clock distribution in +3.3 V or +2.5 V systems.
2. Features
s 100 ps device-to-device skew
s 25 ps within device skew
s 400 ps typical propagation delay
s Maximum frequency > 2 GHz (typical)
s Contains temperature compensation
s PECL and HSTL mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
s NECL mode: VCC = 0 V with VEE = −2.375 V to −3.8 V
s LVDS input compatible
s Open input default state.
1 page  
Philips Semiconductors
PCKEP14
2.5 V/3.3 V 1:5 differential ECL/PECwLw/wH.DSaTtLaSchleoectk4Ud.croivmer
8. Limiting values
Table 5: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VCC PECL mode power supply
VEE NECL mode power supply
VI PECL mode input voltage
NECL mode input voltage
Iout output current
VEE = 0 V
VCC = 0 V
VEE = 0 V; VI ≤ VCC
VCC = 0 V; VI ≥ VEE
continuous
surge
IBB
Tamb
Tstg
Rth(j-a)
VBB source current
operating ambient temperature
storage temperature range
thermal resistance from junction to ambient
0 LFPM
500 LFPM
Rth(j-c)
Tsld
thermal resistance from junction to case
soldering temperature
9. Static characteristics
Min Max Unit
- 4.1 V
- −4.1 V
- 4.1 V
- −4.1 V
- 50 mA
- 100 mA
0 0.1 mA
−40 +85 °C
−65
+150
°C
- 140 °C/W
- 100 °C/W
23 41 °C/W
- 265 °C
Table 6: PECL DC characteristics[1]
VCC = 2.5 V; VEE = 0 V [2]
Symbol Parameter
Conditions
Tamb = −40 °C
Tamb = +25 °C
Tamb = +85 °C Unit
Min Typ Max Min Typ Max Min Typ Max
IEE power supply current
VOH HIGH-level output
voltage
45 60 75 45 60 75 45 60 75 mA
[3] 1355 1480 1605 1355 1500 1605 1355 1510 1605 mV
VOL
VIH
VIL
VIHCMR
LOW-level output voltage
[3] 555 720
HIGH-level input voltage single-ended
1335 -
LOW-level input voltage single-ended
555 -
HIGH-level input voltage,
common mode range
(differential)
[4] 1.2 -
805 555 700
1620 1335 -
875 555 -
2.5 1.2 -
805 555 710
1620 1275 -
875 555 -
2.5 1.2 -
805 mV
1620 mV
875 mV
2.5 V
IIH HIGH-level input current
IIL LOW-level input current CLK
CLK
--
0.5 -
−150 -
150 -
-
- 0.5 -
- −150 -
150 -
-
- 0.5 -
- −150 -
150 µA
- µA
- µA
VBB output reference voltage
1075 1165 1265 1065 1165 1265 1085 1180 1270 mV
[1] Devices are designed to meet the DC specifications shown in this table, after thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit board and transverse air flow greater than 500 LFPM is maintained.
[2] Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −1.3 V.
[3] All loading with 50 Ω to VCC − 2 V.
[4] VIHCMR(min) varies 1:1 with VEE, VIHCMR(max) varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the
differential input signal.
9397 750 09565
Product data
Rev. 01 — 30 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 15
5 Page 
Philips Semiconductors
PCKEP14
2.5 V/3.3 V 1:5 differential ECL/PECwLw/wH.DSaTtLaSchleoectk4Ud.croivmer
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
y
Z
20
D
c
11
EA
X
HE v M A
pin 1 index
1
e
10
wM
bp
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
6.6
6.4
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
EIAJ
SOT360-1
MO-153
L Lp Q
1.0
0.75
0.50
0.4
0.3
vwy
0.2 0.13 0.1
Z (1)
0.5
0.2
θ
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
99-12-27
Fig 7. TSSOP20 package outline (SOT360-1).
9397 750 09565
Product data
Rev. 01 — 30 October 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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