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PDF IR3506 Data sheet ( Hoja de datos )

Número de pieza IR3506
Descripción Phase IC Combined
Fabricantes International Rectifier 
Logotipo International Rectifier Logotipo



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No Preview Available ! IR3506 Hoja de datos, Descripción, Manual

IR3506
DATA SHEET
XPHASE3TM DDR & VTT PHASE IC
DESCRIPTION
The IR3506 Phase IC combined with IR3522 xPHASE3TM Control ICs implements a full featured DDR3 power
solution. The IR3522 provides control functions for both the VDDR and VTT power rails and interfaces with any
number of IR3506 Phase ICs each driving and monitoring a single phase to power any number of DDR3
DIMMs. The xPHASE3TM architecture delivers a power supply that is smaller, more flexible, and easier to
design while providing higher efficiency than conventional approaches.
FEATURES
Power State Indicator (PSI) interface provides the capability to maximize efficiency at light loads
Anti-bias circuitry
7V/2A gate drivers (4A GATEL sink current)
Support loss-less inductor current sensing
Phase delay DFF bypassed during PSI assertion mode to improve output ripple performance
Over-current protection during PSI assertion mode operation
Integrated boot-strap synchronous PFET
Only four IC related external components per phase
3 wire analog bus connects Control and Phase ICs (VDAC, Error Amp, IOUT)
3 wire digital bus for accurate daisy-chain phase timing control without external components
Debugging function isolates phase IC from the converter
Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
Single-wire bidirectional average current sharing
Soft-stop turn-off to insure VDDR and Vtt tracking
Small thermally enhanced 16L 3 x 3mm MLPQ package
RoHS Compliant
www.DaAtaPSPheLetI4CU.AcoTmION CIRCUIT
12V
CCS
RCS
7 Wire
Bus to
Control
IC
VCCL
Page 1 of 21
U1
1 IOUT
SW 12
2
3
IR3506
DACIN PHASE GATEH
LGND IC
BOOST
11
10
CBST
4 PHSIN
VCCL 9
U11
U12
L
CVCCL
CIN
VOUT+
COUT
VOUT-
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IR3506 pdf
IR3506
PARAMETER
TEST CONDITION
Diode Emulation Preset Comparator
Threshold Voltage
Step V(IOUT) up until GATEL drives
high. Compare to V(VCCL)
75 % Regulation Comparator
Threshold Voltage
The ratio of V(CSIN-) / V(DACIN), above
which diode emulation cannot occur.
Negative Current Comparator
Input Offset Voltage
Note 1
Propagation Delay Time
Step V(CSIN+) – V(CSIN-) from positive
to negative while V(IOUT) = VCCL.
Measure time to V(GATEL) < 1V.
Bootstrap Diode
Forward Voltage
I(BOOST) = 30mA, VCCL=6.8V
Debug Comparator
Threshold Voltage
Compare to V(VCCL)
General
VCCL Supply Current
BOOST Supply Current
4.75V V(BOOST)-V(SW) 8V
DACIN Bias Current
SW Floating Voltage
MIN
-1.0
63
-16
30
360
-1.6
4.2
0.5
-1.5
0.1
Note 1: Guaranteed by design, but not tested in production
TYP
-0.8
74
0
200
520
-1.4
10
1.5
-0.75
0.3
MAX UNIT
-0.4 V
85 %
16 mV
380 ns
960
-1.2
16.1
3
1
0.4
mV
V
mA
mA
µA
mA
www.DataSheet4U.com
Page 5 of 21
V3.02

5 Page





IR3506 arduino
IR3506
IR3506 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3506 is shown in Figure 5, and specific features are discussed in the following sections.
CLKIN
PHSIN
1
CAL
PHSIN
15
PHASE
DELAY
VCCL
PHSOUT
EAIN
IOUT
www.DataSheet4U.com
DACIN
LGND
PWM COMPARATOR
GATE
EAI N
-
PWM PWM DRIVERS
+
VCCL
RMPOUT
VCCL PWM RESET
PHSIN
CALIBRATION
PWM RAMP
GENERATOR
NON-
OVERLAP
CIRCUIT
VCCL
DACIN +
-
SHARE_ADJ
DEBUG OFF
(LOW=OPEN)
DACIN-SHARE_ADJ
VCCL
0.8V
DIODE EMULATION
PRESET COMPARATOR
- DE_PRESET
+
GATEL
Disable
DIODE
EMULATION
PRESET ENABLE
LATCH
GATEs
Disable
DEBUG
COMPARATOR
0.15V
SHARE
ADJUST
AMPLIFIER
NEGATIVE CURRENT
COMPARATOR
-
3K +
CAL
DACIN
IROSC
75% REGULATION COMPARATOR
75PCT_REG
CURRENT SENSE
AMPLIFIER
IROSC
+
DACIN
CSAOUT
+
X
0.75
-
X32.5
+
CALIBRATION
PH SI N
PSI
1V
PSI
COMPARATOR
-
+
610mV
510mV
500K
BOOST
GATEH
SW
VCCL
GATEL
PGND
CSIN-
CSIN+
PSI
Figure 5 Block diagram
Tri-State Gate Drivers
The gate drivers can deliver up to 2A peak current (4A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
under voltage or output overload.
Page 11 of 21
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