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PDF IR3527 Data sheet ( Hoja de datos )
| Número de pieza | IR3527 | |
| Descripción | Dual Phase IC Combined | |
| Fabricantes | International Rectifier | |
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IR3527
DATA SHEET
XPHASE3TM DUAL PHASE IC
DESCRIPTION
The IR3527 Dual Phase IC combined with an IR XPhase3TM Control IC provides a full featured and flexible
way to implement multiphase power solutions. The Control IC provides overall system control and interfaces
with any number of IR3527 Phase ICs which each drive and monitor 2 phases of a Synchronous Buck
converter.
The IR3527 implement an independent power savings function for each power stage and sequential phase
timing for use in single output multiphase converters. When power saving mode is enabled, the power stage
will disable its output thus eliminating its switching loss while proper converter operation is maintained by the
single power stage or in conjunction with other converter power stages. The IR3527 current sense amplifiers
remain active when in power savings to support adaptive voltage positioning.
FEATURES
x 7V/1.3A gate drivers (2.6A GATEL sink current)
x Converter output voltage up to 5.1 V (Limited to VCCL-1.4V)
x Loss-less inductor current sensing
x Feed-forward voltage mode control
x Integrated boot-strap synchronous PFET
x Self-calibration of PWM ramp, current sense amplifier, and current share amplifier
x Single-wire bidirectional average current sharing
x Only three external components per phase, plus common decoupling capacitors
x Power State Indicator (PSI) interface provides the capability to maximize the efficiency at light loads.
x Debugging function isolates phase from the converter
x Small thermally enhanced 24L 4 x 4mm MLPQ package
x RoHS compliant
VIN (12V)
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CCS1
RCS1
CCS2
RCS2
3 Wire
Analog
Bus
Power
Savings
Control
3 Wire
Digital
Phase
Timing
IC Bias
(7V)
Page 1 of 20
1 CSIN1+
2 EAIN
3 ISHARE
4 DACIN
5 PSI1
6 PSI2
IR3527 DUAL
PHASE IC
BOOST2
VCCL2
GATEL2
PGND
GATEL1
VCCL1
18
17
16
15
14
13
CBST2
CBST1
L2
L1
CVCCL
Figure 1 – IR3527 Application Circuit
VOUT+
C OU T
VOUT-
CIN
‘
V3.0
1 page  
IR3527
PARAMETER
GATELx low to GATEHx
high delay
GATEHx low to GATELx
high delay
Disable Pull-Down
Resistance
Clock & Daisy Chain
CLKIN Threshold
CLKIN Bias Current
CLKIN Phase Delay
PHSIN Threshold
PHSOUT Propagation
Delay
PHSIN Pull-Down
Resistance
PHSOUT High Voltage
PHSOUT Low Voltage
PWM Comparators
PWM Ramp Slope
EAIN Bias Current
Minimum Pulse Width
Minimum GATEHx Turn-off
Time
www.DataSheOet4VUP.coCmomparator
OVP Threshold
Propagation Delay
Body Brake Comparator
Threshold Voltage with
EAIN falling.
Threshold Voltage with
EAIN rising.
Hysteresis
Propagation Delay
TEST CONDITION
BOOSTx = VCCLx = 7V, SWx = PGND = 0V,
measure time from GATELx falling to 1V to
GATEHx rising to 1V
BOOSTx = VCCLx = 7V, SWx = PGND =
0V, measure time from GATEHx falling to 1V
to GATELx rising to 1V
Note 1
MIN
10
10
30
Compare to V(VCCLx)
CLKIN = V(VCCLx)
Measure time from CLKIN<1V to
GATEHx>1V
Compare to V(VCCLx)
Measure time from CLKIN > (VCCLx*50%)
to PHSOUT>(VCCLx*50%). 10pF@125oC
I(PHSOUT) = -5mA, measure VCCLx –
PHSOUT
I(PHSOUT) = 5mA
40
-0.5
40
35
4
30
2
Vin=12V
0 EAIN 3V
Note 1
42
-5
20
Step V(ISHARE) up until GATELx drives
high. Compare to V(VCCLx)
V(VCCLx)=5V, Step V(ISHARE) up from
V(DACIN) to V(VCCLx). Measure time to
V(GATELx)>4V.
Measured relative to PWM Ramp Floor
Voltage
Measured relative to PWM Ramp Floor
Voltage
VCCLx = 5V. Measure time from EAIN <
V(DACIN) (200mV overdrive) to GATELx
transition to < 4V.
-1.0
15
-340
-240
70
40
TYP
20
20
80
45
0.0
75
50
15
100
0.6
0.4
52.5
-0.3
65
80
-0.8
40
-235
-135
105
65
MAX UNIT
40 ns
40 ns
130 N
57 %
0.5 PA
125 ns
55 %
35 ns
170 N
V
2V
mV/
57 %DC
5 PA
75 ns
160 ns
-0.4 V
70 ns
-130
-30
130
90
mV
mV
mV
ns
Page 5 of 20
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IR3527
by the control IC for voltage positioning and current limit protection. The input offset of this amplifier is calibrated to
+/- 1mV in order to reduce the current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on ISHARE bus with a frequency of fsw/(32*28) in a multiphase architecture.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC.
The output of the current sense amplifier is compared with the average current at the share bus. If current in a
phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of
the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average
current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing
its duty cycle and output current. The current share amplifier is internally compensated so that the crossover
frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact.
IR3527 THEORY OF OPERATION
Block Diagram
A detailed IR3527 block diagram is enclosed (Figure 6) to help clearly illustrate the following theory of operation.
Tri-State Gate Drivers
The gate drivers can deliver up to 1.3A peak current (2.6A sink current for bottom driver). An adaptive non-overlap
circuit monitors the voltage on the GATEH and GATEL pins to prevent MOSFET shoot-through current while
minimizing body diode conduction. The non-overlap latch is added to eliminate the error triggering caused by the
switching noise. An enable signal is provided by the control IC to the phase IC without the addition of a dedicated
signal line. The error amplifier output of the control IC drives low in response to any fault condition such as VCCL
under voltage or output overload. The IR3527 Body BrakingTM comparator detects this and drives both gate outputs
low. This tri-state operation prevents negative inductor current and negative output voltage during power-down.
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A synchronous rectification disable comparator is used to detect converter CSIN- pin voltage, which represents
local converter output voltage. If the voltage is below 75% of VDAC and negative current is detected, GATEL drives
low, which disables synchronous rectification and eliminates negative current during power-up.
The gate drivers pull low if the supply voltages are below the normal operating range. An 80k UHVLVWRU LV FRQQHFWHG
across the GATEH/GATEL and PGND pins to prevent the GATEH/GATEL voltage from rising due to leakage or
other causes under these conditions.
Page 11 of 20
V3.0
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IR3527.PDF ] | |
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