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PDF VN750PEP Data sheet ( Hoja de datos )
| Número de pieza | VN750PEP | |
| Descripción | HIGH SIDE DRIVER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de VN750PEP (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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® VN750PEP
TYPE
VN750PEP
RDS(on)
60 mΩ
IOUT
6A
VCC
36 V
s CMOS COMPATIBLE INPUT
s ON STATE OPEN LOAD DETECTION
s OFF STATE OPEN LOAD DETECTION
s SHORTED LOAD PROTECTION
s UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
s PROTECTION AGAINST LOSS OF GROUND
s VERY LOW STAND-BY CURRENT
s REVERSE BATTERY PROTECTION (*)
DESCRIPTION
The VN750PEP is a monolithic device designed in
STMicroelectronics VIPower M0-3 Technology,
intended for driving any kind of load with one side
connected to ground.
Active VCC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart protect the device against overload.
HIGH SIDE DRIVER
TARGET SPECIFICATION
PowerSSO-12
ORDER CODES
PACKAGE
TUBE
T&R
PowerSSO-12 VN750PEP VN750PEP13TR
The device detects open load condition both is on
and off state. Output shorted to VCC is detected in
the off state. Device automatically turns off in case
of ground pin disconnection.
BLOCK DIAGRAM
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GND
VCC
CLAMP
INPUT
LOGIC
STATUS
OVERTEMPERATURE
DETECTION
OVERVOLTAGE
DETECTION
UNDERVOLTAGE
DETECTION
Power CLAMP
DRIVER
CURRENT LIMITER
ON STATE OPENLOAD
DETECTION
OFF STATE OPENLOAD
AND OUTPUT SHORTED TO VCC
DETECTION
VCC
OUTPUT
(*) See application schematic at page 8
October 2003 - Revision 1.2 (Working document)
1/14
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
1 page  
Switching time Waveforms
VOUT
80%
dVOUT/dt(on)
VIN td(on)
VN750PEP
90%
10%
td(off)
dVOUT/dt(off)
t
TRUTH TABLE
CONDITIONS
Normal Operation
Current Limitation
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Overtemperature
Undervoltage
Overvoltage
Output Voltage > VOL
Output Current < IOL
INPUT
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
t
OUTPUT
L
H
L
X
X
L
L
L
L
L
L
H
H
L
H
STATUS
H
H
H
(Tj < TTSD) H
(Tj > TTSD) L
H
L
X
X
H
H
L
H
H
L
5/14
5 Page 
On State Resistance Vs Tcase
TBD
On State Resistance Vs VCC
VN750PEP
TBD
Openload On State Detection Threshold
Input High Level
TBD
TBD
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Input Low Level
Input Hysteresis Voltage
TBD
TBD
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet VN750PEP.PDF ] | |
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