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PDF IR3710MTRPBF Data sheet ( Hoja de datos )
| Número de pieza | IR3710MTRPBF | |
| Descripción | SYNCHRONOUS BUCK REGULATOR | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Data Sheet No. PD60367
IR3710MTRPBF
WIDE INPUT AND OUTPUT, SYNCHRONOUS BUCK REGULATOR
FEATURES
Input Voltage Range: 3V to 28V
Output Voltage Range: 0.5V to 12V
Constant On-Time control
Excellent Efficiency at very low output current levels
Gate drive charge pump option to maximize
efficiency at higher output current levels
Compensation Loop not Required
Programmable switching frequency, soft start, and
over current protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Enable Input with Voltage Monitoring Capability
Pre-bias Start Up
Under/Over Voltage Fault Protection
16pin 3x3 MLPQ lead free package
RoHS compliant
DESCRIPTION
The IR3710 is a single-phase sync-buck PWM
controller optimized for efficiency in high performance
portable electronics. The switching modulator uses
constant on-time control. Constant on-time with diode
emulation provides the highest light-load efficiency
required for all.
Programmable switching frequency, soft start, and over
current protection allows for a very flexible solution
suitable for many different applications. The
combination of the gate drive charge pump option and
constant on time control allow efficiency optimization in
the whole output current range, making this device an
ideal choice for battery powered applications.
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut down,
power good output, and enable input with voltage
monitoring capability.
APPLICATION CIRCUIT
Enhanced Gate Drive Application Circuit:
V5
www.DataSheet4U.com
V3.3
D1
6.2k 10k
RISET
D2 DBOOT
C1
CPO
PVCC
FF
BOOT
VCC
UGATE
EN IR3710
PHASE
FCCM
PGOOD
ISET
LGATE
PGND
SS
CSS
GND
FB
VIN
RFF
CBOOT
L
R1
R2
VOUT
COUT
ORDERING INFORMATION
Package Description
Pin Count
IR3710MTRPbF
16
Page 1 of 20
www.irf.com
IR Confidential
Parts Per Reel
4000
1/23/09
1 page  
IR3710MTRPBF
IC PIN ORDER AND DESCRIPTION
NAME
BOOT
FF
EN
ISET
PGOOD
GND
FCCM
FB
SS
VCC
CPO
PVCC
LGATE
PGND
PHASE
UGATE
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O LEVEL
VIN +PVCC
VIN
3.3V
32V
3.3V
Reference
3.3V
3.3V
3.3V
3.3V
3.3V
7.4V
PVCC
Reference
VIN
VIN + V5
DESCRIPTION
Bootstrapped gate drive supply – connect a capacitor to PHASE
Input voltage feed forward – sets on-time with a resistor to VIN
Enable input; EN = LOW inhibits GATE pulses
Current limit setting with a resistor to PH pin
Power good – pull up to 3.3V
Bias return and signal reference
Force continuous conduction mode when pulled up to VCC
Feedback input
Set soft start slew-rate with a capacitor to GND
IC bias supply
Charge Pump Output
Gate drive supply
Lower gate drive for synchronous MOSFET
Power return – connect to source of synchronous MOSFET
Phase node (or switching node) of MOSFET half bridge
Upper gate drive for control MOSFET
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BOOT 1
FF 2
EN 3
ISET 4
GND
12 PVCC
11 CPO
10 VCC
9 SS
PGOOD GND FCCM FB
θJA = 49 oC/W
θJC = 4 oC/W
Page 5 of 20
www.irf.com
IR Confidential
1/23/09
5 Page 
IR3710MTRPBF
FUNCTIONAL DESCRIPTION
Refer to Block Diagram
ON-TIME GENERATOR
The PWM comparator initiates a SET signal (PWM
pulse) when the FB pin falls below lower of the
reference (VREF) or soft start (SS) voltage.
The PWM on-time duration is programmed with an
external resistor (RFF) from the input supply (VIN) to
the FF pin. The simplified equation for RFF is shown
in the equation 1. The FF pin is held to an internal
reference after EN goes HIGH. A copy of the current
in RFF charges a timing capacitor, which set the on-
time duration, as shown in equation 2.
RFF
=
1V
⋅
VOUT
20 pF ⋅FSW
(1)
TON
=
RFF
⋅1V ⋅20
VIN
pF
(2)
SOFT START
An internal 10uA current source charges external
capacitor on the SS pin to set the output voltage slew
rate during the soft start interval. The output voltage
reaches regulation when the FB pin is above the
under voltage threshold and the UV# = HIGH. Once
the voltage on the SS pin is above the PGOOD delay
threshold, the combination of the SSDelay and UV#
signals release the PGOOD pin. With EN = LOW, the
capacitor voltage and SS pin is held to the FB pin
voltage.
www.DOatVaSEheRet4CUU.coRmRENT MONITOR
IR3710 monitors the output current every switching
cycle. The voltage across the synchronous
MOSFET, VPHASE is monitored for over current and
zero crossing. The minimum LGATE interval allows
time to sample VPHASE.
The over current trip point is programmed with a
resistor from ISET to PHASE pins, as shown in
equation 3. When over current is detected, output
gates are tri-state and SS voltage is pulled to 0V. A
new soft start cycle begins right after. If there is three
(3) consecutive OC events, IR3710 will disable
switching. Toggling VCC or EN will allow next start
up.
RSET
=
RDSON
20
⋅ IOC
µA
(3)
GATE DRIVE LOGIC
The gate drive logic features adaptive dead time,
diode emulation, and a minimum lower gate interval.
An adaptive dead time prevents the simultaneous
conduction of the upper and lower MOSFETs. The
lower gate voltage must be below approximately 1V
after PWM goes HIGH before the upper MOSFET
can be gated on. Also the upper gate voltage, the
difference voltage between UGATE and PHASE,
must be below approximately 1V after PWM goes
LOW and before the lower MOSFET can be gated
on.
Diode emulation is enabled after PGOOD = HIGH
when FCCM is LOW. The control MOSFET is gated
on after the adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the adaptive
delay for PWM = LOW. The lower MOSFET is driven
‘off’ when the signal ZCROSS indicates that the inductor
current reverses as detected by the PHASE voltage
crossing the zero current threshold. The synchronous
MOSFET stays ‘off’ until the next PWM falling edge.
When FCCM = HIGH, forced continuous current
condition is selected. The control MOSFET is gated
on after the adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the adaptive
delay for PWM = LOW.
The synchronous MOSFET gate is driven on for a
minimum duration. This minimum duration allows
time to recharge the bootstrap capacitor and allows
the current monitor to sample the phase voltage.
CONTROL LOGIC
The control logic monitors input power sources for
supply voltage conditions, sequences the converter
through the soft-start and protective modes, and
indicates output voltage status on the PGOOD pin.
VCC and PVCC pins are continuously monitored.
IR3710 is disabled if either of these voltages drops
below falling thresholds.
IR3710 will initiate a soft start when the VCC and
PVCC are in the normal range and the EN pin =
HIGH. In the event of a sustained overload, a
counter keep track of 4 consecutive soft-start cycles
and disables IR3710.
If the overload is momentary and output voltage is
within regulation before 4 consecutive soft-start
cycles, PGOOD transitions HIGH to reset the
counter.
OVER VOLTAGE PROTECTION
IR3710 monitors the voltage at FB node. If the FB
voltage is above the threshold of over voltage, the
gates are turn off and pulls PGOOD signal low.
Toggling VCC or EN will allow next start up.
Page 11 of 20
www.irf.com
IR Confidential
1/23/09
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IR3710MTRPBF.PDF ] | |
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