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ICS8516 fiches techniques PDF

Integrated Circuit Systems - 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP

Numéro de référence ICS8516
Description 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Fabricant Integrated Circuit Systems 
Logo Integrated Circuit Systems 





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ICS8516 fiche technique
Integrated
Circuit
Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS8516 is a low skew, high performance Sixteen differential LVDS outputs
1-to-16 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS ™
family of High Performance Clock Solutions from
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
ICS. The ICS8516 CLK, nCLK pair can accept
any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling
(LVDS), the ICS8516 provides a low power, low noise, point-
Maximum output frequency: 700MHz
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
to-point solution for distributing clock signals over controlled Translates any single-ended input signal to LVDS
impedances of 100Ω.
with resistor bias on nCLK input
Dual output enable inputs allow the ICS8516 to be used in a Multiple output enable inputs for disabling unused
1-to-16 or 1-to-8 input/output mode.
outputs in reduced fanout applications
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
LVDS compatible
Output skew: 90ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 2.4ns (maximum)
Additive phase jitter, RMS: 148fs (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
www.DataSheet4U.com
CLK
nCLK
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
8516FY
OE1
OE2
PIN ASSIGNMENT
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
VDD
nQ5
Q5
nQ4
Q4
VDD
GND
nQ3
Q3
nQ2
Q2
VDD
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6
7
ICS8516
31
30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VDD
nQ10
Q10
nQ11
Q11
VDD
GND
nQ12
Q12
nQ13
Q13
VDD
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B FEBRUARY 21, 2006

PagesPages 15
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