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PDF ICS8512061I Data sheet ( Hoja de datos )
| Número de pieza | ICS8512061I | |
| Descripción | SINGLE CHANNEL 0.7V DIFFERENTIALTO-LVTTL TRANSCEIVER | |
| Fabricantes | Integrated Device Technology | |
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SINGLE CHANNEL 0.7V DIFFERENTIAL-
TO-LVTTL TRANSCEIVER
General Description
The ICS8512061I is a transceiver which can
ICS interchange data across multipoint data bus
HiPerClockS™ structures.
The device has an LVTTL driver and one HCSL
receiver driver. It translates between LVTTL signals
and HCSL signals.
Applications
Backplane Transmission
Telecommunication System
Data Communications
ATCA Clock Distribution
ICS8512061I
Features
• One HCSL output pair and one LVCMOS/LVTTL output
• One single-ended LVCMOS/LVTTL signal input
• LVTTL I/O signal: up to 250MHz
• HCSL interface pins in high impedance state when the device is
powered down
• Power-up and power-down glitch-free
• Additive Phase Jitter, RMS: 0.23ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
www.DaQtaBSheet4U.com
IREF
IN Pullup
DIR_SEL Pulldown
HCSL
Interface
QA
nQA
Pin Assignment
GND
QB
DIR_SEL
IN
1
2
3
4
8 QA
7 nQA
6 VDD
5 IREF
ICS8512061I
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
IDT™ / ICS™ TRANSCEIVER
1 ICS8512061AGI REV. B NOVEMBER 19, 2008
1 page  
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Additive Phase Jitter (HCSL)
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.29ps (typical)
www.DataSheet4U.com
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ TRANSCEIVER
5 ICS8512061AGI REV. B NOVEMBER 19, 2008
5 Page 
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Power Considerations (HCSL Outputs)
This section provides information on power dissipation and junction temperature for the ICS8512061I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW
• Power (outputs)MAX = 46.8mW/Loaded Output pair
Total Power_MAX = 72mW + 46.8mW = 118.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
www.DataSh8e5e°tC4U+.c0o.m119W * 129.5°C/W = 100.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5A. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
1
125.5
2.5
123.5
IDT™ / ICS™ TRANSCEIVER
11 ICS8512061AGI REV. B NOVEMBER 19, 2008
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ICS8512061I.PDF ] | |
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