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PDF WCMA4016U1X Data sheet ( Hoja de datos )
| Número de pieza | WCMA4016U1X | |
| Descripción | 256K x 16 Static RAM | |
| Fabricantes | Weida Semiconductor | |
| Logotipo |  |
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Y62147BV
L™
WCMA4016U1X
Features
• Low voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE1 and CE2 and OE fea-
tures
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description[1]
The WCMA4016U1X is a high-performance CMOS static
RAM organized as 262,144 words by 16 bits. This device
features advanced circuit design to provide ultra-low active
current and standby current. This is ideal for providing more
battery life in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99% when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or
Logic Block Diagram
256K x 16 Static RAM
both BHE and BLE are HIGH). The input/output pins (I/O0
through I/O15) are placed in a high-impedance state when:
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or during a write operation (CE1
LOW, CE2 HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O0 to I/O7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on I/O8 to I/O15. See the truth table at the back of this
datasheet for a complete description of read and write modes.
Pin Configurations
FBGA (Top View)
12 34 56
A9
A8
A7
www.DaAta6Sheet4U.com
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K × 16
RAM Array
2048 × 2048
COLUMN DECODER
I/O0 – I/O7
I/O8 – I/O15
BLE OE A0 A1 A2 CE2
I/O8 BHE A3 A4 CE I/O0
I/O9 I/O10 A5 A6 I/O1 I/O2
VSS I/O11 A17 A7 I/O3 VCC
VCC I/O12 NC A16 I/O4 VSS
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC A12 A13 WE I/O7
NC A8 A9 A10 A11 NC
A
B
C
D
E
F
G
H
Power -Down
Circuit
.
BHE
BLE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Weida Semiconductor, Inc.
1 page  
Switching Characteristics Over the Operating Range[6] (continued)
tBW
tSD
tHD
tHZWE
tLZWE
Parameter
Description
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[7, 9]
WE HIGH to Low Z[7]
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[12, 13]
ADDRESS
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
tRC
WCMA4016U1X
70 ns
Min.
Max.
60
30
0
25
10
Unit
ns
ns
ns
ns
ns
DATA VALID
Read Cycle 2 (OE Controlled)[13, 14]
ADDRESS
CE1
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BHE/BLE
OE
DATA OUT
VCC
SUPPLY
CURRENT
tRC
tACE
tDBE
tLZBE
tDOE
tLZOE
HIGH IMPEDANCE
tLZCE
tPU
50%
tPD
tHZCE
tHZBE
tHZOE
DATA VALID
HIGH
IMPEDANCE
50%
ICC
ISB
Notes:
12. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet WCMA4016U1X.PDF ] | |
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