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PDF HD64F2345 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2345 | |
| Descripción | H8S/2345 F-ZTAT Hardware Manual | |
| Fabricantes | Hitachi Semiconductor | |
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H8S/2345 Series
H8S/2345, H8S/2344, H8S/2343,
H8S/2341, H8S/2340
H8S/2345 F-ZTATTM
Hardware Manual
www.DataSheet4U.com
ADE-602-129A
Rev. 2.0
1/12/98
Hitachi, Ltd.
1 page  
Page
Item
Revision
533 16.1 Overview
Description amended (Information on
newly added products)
534
Figure 16.1 Block Diagram of RAM
Title of figure amended
(H8S/2345, Advanced Mode)
535 16.3 Operation
Description amended (Information on
newly added products)
Whole of Section 17 ROM
section 17 New flash memory description added, complete revision of section contents and layout
Whole of Section 20 Electrical Characteristics
section 20 Previous text used as electrical characteristics for ZTAT, mask ROM, and ROMless
versions; new F-ZTAT version electrical characteristics added.
"Preliminary" notation deleted and "TBD" replaced with values for ZTAT, mask ROM,
and ROMless versions.
666 Figure 20.9 Reset Input Timing
Amended
669 Figure 20.12 Basic Bus Timing (Three- Amended (t specification)
WDS
State Access)
675 Figure 20.24 SCK Clock Input Timing
677 to 752 Appendix A Instruction Set
Amended (t specification)
SCKW
Amended (Replaced with latest version)
753 to 759 B.1 Addresses
Amended (Addition of registers used by F-
ZTAT version)
760 to 858 B.2 Functions
Amended
• Addition of registers used by F-ZTAT
version
• Amendment of note on interrupt priority
registers A-K
893 Table F.1 H8S/2345 Series Product Code Amended (Information on newly added
www.DataSheLeint4eUu.pcom
products)
5 Page 
Section 7 Data Transfer Controller .............................................................................. 173
7.1 Overview............................................................................................................................ 173
7.1.1 Features ................................................................................................................ 173
7.1.2 Block Diagram...................................................................................................... 174
7.1.3 Register Configuration ......................................................................................... 175
7.2 Register Descriptions......................................................................................................... 176
7.2.1 DTC Mode Register A (MRA)............................................................................. 176
7.2.2 DTC Mode Register B (MRB) ............................................................................. 178
7.2.3 DTC Source Address Register (SAR) .................................................................. 179
7.2.4 DTC Destination Address Register (DAR) .......................................................... 179
7.2.5 DTC Transfer Count Register A (CRA) .............................................................. 179
7.2.6 DTC Transfer Count Register B (CRB) ............................................................... 180
7.2.7 DTC Enable Registers (DTCER) ......................................................................... 180
7.2.8 DTC Vector Register (DTVECR) ........................................................................ 181
7.2.9 Module Stop Control Register (MSTPCR) .......................................................... 182
7.3 Operation ........................................................................................................................... 183
7.3.1 Overview .............................................................................................................. 183
7.3.2 Activation Sources................................................................................................ 185
7.3.3 DTC Vector Table ................................................................................................ 186
7.3.4 Location of Register Information in Address Space ............................................ 189
7.3.5 Normal Mode........................................................................................................ 190
7.3.6 Repeat Mode ........................................................................................................ 191
7.3.7 Block Transfer Mode............................................................................................ 192
7.3.8 Chain Transfer...................................................................................................... 194
7.3.9 Operation Timing ................................................................................................. 195
7.3.10 Number of DTC Execution States........................................................................ 196
7.3.11 Procedures for Using DTC ................................................................................... 198
7.3.12 Examples of Use of the DTC................................................................................ 199
7.4 Interrupts............................................................................................................................ 201
7w.5ww.DUatsaaSgheeNet4oUte.cso..m..................................................................................................................... 201
Section 8 I/O Ports ............................................................................................................ 203
8.1 Overview............................................................................................................................ 203
8.2 Port 1.................................................................................................................................. 208
8.2.1 Overview .............................................................................................................. 208
8.2.2 Register Configuration ......................................................................................... 209
8.2.3 Pin Functions........................................................................................................ 210
8.3 Port 2.................................................................................................................................. 219
8.3.1 Overview .............................................................................................................. 219
8.3.2 Register Configuration ......................................................................................... 219
8.3.3 Pin Functions........................................................................................................ 221
8.4 Port 3.................................................................................................................................. 230
8.4.1 Overview .............................................................................................................. 230
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64F2345.PDF ] | |
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