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PDF UJA1076 Data sheet ( Hoja de datos )
| Número de pieza | UJA1076 | |
| Descripción | High-speed CAN Core System Basis Chip | |
| Fabricantes | NXP Semiconductors | |
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UJA1076
High-speed CAN core system basis chip
Rev. 01 — 1 December 2009
Product data sheet
1. General description
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The UJA1076 core System Basis Chip (SBC) replaces the basic discrete components
commonly found in Electronic Control Units (ECU) with a high-speed Controller Area
Network (CAN).
The UJA1076 supports the networking applications used to control power and sensor
peripherals by using a high-speed CAN as the main network interface.
The core SBC contains the following integrated devices:
• High-speed CAN transceiver, inter-operable and downward compatible with CAN
transceiver TJA1042, and compatible with the ISO 11898-2 and ISO 11898-5
standards
• Advanced independent watchdog (UJA1076/xx/WD versions)
• 250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
• Separate voltage regulator for supplying the on-board CAN transceiver
• Serial peripheral interface (full duplex)
• 2 local wake-up input ports
• Limp-home output port
In addition to the advantages gained from integrating these common ECU functions in a
single package, the core SBC offers an intelligent combination of system-specific
functions such as:
• Advanced low-power concept
• Safe and controlled system start-up behavior
• Detailed status reporting on system and sub-system levels
The UJA1076 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The SBC ensures that the microcontroller always starts up
in a controlled manner.
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
UJA1076
High-speed CAN core system basis chip
i.c. 1
i.c. 2
i.c. 3
V1 4
i.c. 5
RSTN 6
INTN 7
EN 8
SDI 9
SDO 10
SCK 11
SCSN 12
TXDC 13
RXDC 14
TEST1 15
WDOFF 16
Fig 2. Pin configuration
UJA1076
32 BAT
31 VEXCTRL
30 TEST2
29 VEXCC
28 WBIAS
27 i.c.
26 i.c.
25 i.c.
24 SPLIT
23 GND
22 CANL
21 CANH
20 V2
19 WAKE2
18 WAKE1
17 LIMP
015aaa109
5.2 Pin description
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Table 2.
Symbol
i.c.
i.c.
i.c.
V1
i.c.
RSTN
INTN
EN
SDI
SDO
SCK
SCSN
TXDC
RXDC
TEST1
WDOFF
LIMP
Pin description
Pin Description
1 internally connected; should be left floating
2 internally connected; should be left floating
3 internally connected; should be left floating
4 voltage regulator output for the microcontroller (5 V or 3.3 V depending on
SBC version)
5 internally connected; should be left floating
6 reset input/output to and from the microcontroller
7 interrupt output to the microcontroller
8 enable output
9 SPI data input
10 SPI data output
11 SPI clock input
12 SPI chip select input
13 CAN transmit data input
14 CAN receive data output
15 test pin; pin should be connected to ground
16 WDOFF pin for deactivating the watchdog
17 limp home output
UJA1076_1
Product data sheet
Rev. 01 — 1 December 2009
© NXP B.V. 2009. All rights reserved.
5 of 45
5 Page 
NXP Semiconductors
UJA1076
High-speed CAN core system basis chip
6.2.3 WD_and_Status register
Table 4. WD_and_Status register
Bit Symbol
Access Power-on Description
default
15:13 A2, A1, A0 R 000 register address
12 RO
R/W 0
access status
0: register set to read/write
1: register set to read only
11 WMC
R/W 0
watchdog mode control
0: Normal mode: watchdog in Window mode; Standby mode: watchdog in
Timeout mode
1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in Off
mode
10:8 NWP[1]
R/W 100
nominal watchdog period
000: 8 ms
001: 16 ms
010: 32 ms
011: 64 ms
100: 128 ms
101: 256 ms
110: 1024 ms
111: 4096 ms
7 SWR/WOS R/W -
software reset/watchdog off status
0: WDOFF pin LOW; watchdog mode determined by bit WMC
1: watchdog disabled due to HIGH level on pin WDOFF; results in software
reset
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R
-
V1 status
0: V1 output voltage above 90 % undervoltage recovery threshold (Vuvr; see
Table 9)
1: V1 output voltage below 90 % undervoltage detection threshold (Vuvd; see
Table 9)
5 V2S
R-
V2 status
0: V2 output voltage above undervoltage release threshold (Vuvr; see Table 9)
1: V2 output voltage below undervoltage detection threshold (Vuvd;see
Table 9)
4 WLS1
R
-
wake-up1 status
3 WLS2
R
-
0: WAKE1 input voltage below switching threshold (Vth(sw))
1: WAKE1 input voltage above switching threshold (Vth(sw))
wake-up 2 status
2:0 reserved R
000
0: WAKE2 input voltage below switching threshold (Vth(sw))
1: WAKE2 input voltage above switching threshold (Vth(sw))
[1] Bit NWP is set to it’s default value (100) after a reset.
UJA1076_1
Product data sheet
Rev. 01 — 1 December 2009
© NXP B.V. 2009. All rights reserved.
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